HYB18T512400AF Datasheet, PDF (2/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM

Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
HYB18T512400AF(L), HYB18T512800AF(L), HYB18T512160AF(L)
Revision History: 2007-01, Rev. 1.71
Page
Subjects (major changes since last revision)
All
Qimonda update
All
Adapted internet edition
108
Modified AC Timing Parameters
Previous Revision: 2006-05, Rev. 1.7
57
Changed “Read” to “Write” in condition 4.
57
Removed text “Maximum power up interval for V_DD / V_DDQ is specified
As 20.0 ms. The power interval is defined as the amount of time it takes for V_DD / V_DDQ to power-up From 0 V
to 1.8 V ± 100 mV” from condition 1.
Previous Revision: 2005-08, Rev. 1.6
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
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03062006-CPCN-4867