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HYB18T512400AF Datasheet, PDF (14/58 Pages) Infineon Technologies AG – 512-Mbit DDR2 SDRAM
◁
Internet Data Sheet
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
FIGURE 3
Pin Configuration for × 16 components, PG-TFBGA-84-8









6'' 
.#
66 6 
'4 
6664 
8'0
6'' 4
'4 
6'' 4
'4 
6664 
'4 
6'' 
1&
66 6 
'4 
6664 
/'0
6'' 4
'4 
6'' 4
'4 
6664 
'4 
6' '/
65( )
66 6 
$
666 4
8'46 
6'' 4
%
8'46
666 4 
'4 
&
6'' 4
'4 
6'' 4
'
'4 
666 4 
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(
666 4
/'46 
6'' 4
)
/'46
666 4 
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*
6'' 4
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6'' 4
+
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666 4 
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-
966 '/ &.
6'' 
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:(
.
5$6
&.
2' 7
1&
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$ $3 $
0
$
$
6'' 
66 6 
$
$
1
$
$
$
$
3
$
$
666 
6'' 
$ 
1&
5
1&
1&
03 37 
Notes
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is
data strobe for DQ[7:0]
2. LDM is the data mask signal for DQ[7:0], UDM is the data
mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL. VDDL is
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS,
and VSSQ are isolated on the device.
Rev. 1.71, 2007-01
14
03062006-CPCN-4867
 ▷