XA-SCC Datasheet, PDF (6/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
PIN DESCRIPTIONS
MNEMONIC
LQFP
PIN NO.
TYPE
NAME AND FUNCTION
V_SS
1, 19,
I Ground: 0V reference.
28, 44,
59, 76,
88
V_DD
2, 20,
I Power Supply: This is the power supply voltage for normal, idle, and power down operation.
29, 43,
62, 77,
89
ResetIn
55
I Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their
default states, and the processor to begin execution at the address contained in the reset vector.
WAIT/Size16
52
I Wait/Size16: During Reset, this input determines bus size for boot device (1 = 16 bit boot device,
0 = 8 bit.) During normal operation this is the Wait input (1 = Wait, 0 = Proceed.)
XTALIn
60
I Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock
generator circuits.
XTALOut
61
I Crystal 2: Output from the oscillator amplifier.
CS0
49
O Chip Select 0: This output provides the active low chip select to the boot device (usually ROM or
Flash.) It cannot be connected to DRAM. From reset, it is enabled and mapped to an address range
based at 000000h. It can be remapped to a higher base in the address map (see the Memory Interface
chapter in the XA-SCC User Manual.)
CS1_RAS1
48
O Chip Select 1 , RAS 1: Chip selects 1 through 5 come out of reset disabled. They can be programmed
to function as normal chip selects, or as RAS strobes to DRAM. CS1 can be “swapped” with CS0
(see the SWAP operation and control bit in the Memory Controller chapter of the XA-SCC
User Manual.) CS1 is usually mapped to be based at 000000h eventually, but is capable of being based
anywhere in the 16MB space.
CS2_RAS2
47
O CS2 , RAS 2: Active low chip selects CS1 through CS5 come out of reset disabled. They can be
programmed to function as normal chip selects, or as RAS strobes to DRAM. CS2 through CS5 are
not used with the “SWAP” operation (see Memory Controller chapter in the XA-SCC User Manual.)
They are mappable to any region of the 16MB address space.
CS3_RAS3
46
O CS3, RAS 3: See chip select 2 for description.
see pins 56,57 for 2 more chip
selects
WE
50
O Write Enable: Goes active low during all bus write cycles only.
OE
51
O Output Enable: Goes active low during all bus read cycles only.
BLE_CASL
54
O Byte Low Enable or CAS_Low_Byte: Goes active low during all bus cycles that access D7–D0, read
or write, Generic or DRAM. Functions as CAS during DRAM cycles.
BHE_CASH
53
O Byte High Enable or CAS_High_Byte: Goes active low during all bus cycles that access D15–D8,
read or write, Generic or DRAM. Functions as CAS during DRAM cycles.
ClkOut
45
O Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may be
used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock output
may be disabled by software. WARNING: The capacitive loading on this output must not exceed 40pF.
A19–A0
24–21,
18–3
O Address[19:0]: These address lines output a19–a0 during generic (SRAM etc) bus cycles. DRAMs are
connected only to pins 22,21, 18–10 (pins A17 to A7; see User Manual MIF Chapter for connecting
various DRAM sizes); the appropriate address values are multiplexed onto these 11 pins for RAS and
CAS during DRAM bus cycles.
D15–D0
P0.0¹
P0.1¹
P0.2¹
P0.3¹
P0.4^{1, 2}
42–30,
27–25
90
91
92
93
94
I/O Data[15:0]: Bi-directional data bus, D15–D0.
I/O P0.0_Sync0_BRG0_SDS2: Port 0 Bit 0, or SCC0 Sync input or output, or SCC0 BRG output, or SCC0
TxClk output, or IDL SDS2 output.
I/O P0.1_RTS0_L1RQ: Port0 Bit1 , or SCC0 RTS (Request to send) output, or IDL L1RQ (D Channel
Request) output.
I/O P0.2_CTS0_L1GR: Port 0 Bit2, or SCC0 CTS (Clear to Send) input or IDL L1GR (D Channel Grant)
input
I/O P0.3_CD0_L1SY1: Port 0 Bit 3, or SCC0 Carrier Detect input, or IDL Sync input.
I/O P0.4_TRClk0_SDS1: Port 0 Bit 4, or SCC0 TR clock input, or IDL SDS1 output.
1999 Mar 29
6