XA-SCC Datasheet, PDF (22/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
Receive DMA Channel Modes
The Rx DMA channels have four DMA modes specifically designed
for various applications of the attached SCCs. These modes are
summarized in the following table. For full details on implementation
and use, see the XA-SCC User Manual.
Table 5. Rx DMA Modes Summary
Mode
Byte Count Source
SDLC/HDLC Rx
Chaining
DMA stores byte count in header in
memory with data packet.
Periodic Interrupt
Asynchronous
Character Time Out
Asynchronous
Character Match
Loaded by processor into DMA,
used only to determine the number
of bytes between interrupts.
Processor can infer the byte count
from the DMA address pointer.
Byte Count can be calculated by
software from the DMA address
pointer.
Byte Count can be calculated by
software from the DMA address
pointer.
Maskable Interrupt
At end of received
packet
When Byte Counter
reaches zero and is
reloaded by DMA
hardware from the byte
count register.
If no character is
received within a
specified time out
period, then interrupt.
When matched
character is stored in
memory.
Description
When a complete or aborted SDLC/HDLC
packet has been received, the packet byte count
and status information are stored in memory with
the packet. A maskable interrupt is generated.
The DMA channel runs until commanded to stop
by the processor. It generates a maskable
interrupt once per n bytes, where n is the
number written once into the byte count register
by the processor, thus an interrupt is generated
once every n received bytes.
Processor specifies time out period between
incoming characters. If no character is received
within that time, interrupt is generated.
There are four match registers, each incoming
character is compared to all four registers. When
a matched character is stored in memory by
DMA, a maskable interrupt is generated.
DATA FIFO 3
DATA FIFO 1
DATA FIFO 2
DATA FIFO 0
DMA CONTROL
SEGMENT
BUFFER BASE
BUFFER BOUND
ADDRESS POINTER
BYTE COUNT
FIFO CONTROL
Rx TIME OUT
Rx CHANNEL
1999 Mar 29
DATA FIFO 3
DATA FIFO 1
DATA FIFO 2
DATA FIFO 0
DMA CONTROL
SEGMENT
BUFFER BASE
BUFFER BOUND
ADDRESS POINTER
BYTE COUNT
FIFO CONTROL
Figure 6. Rx and Tx DMA Registers
Tx CHANNEL
SU01127
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