XA-SCC Datasheet, PDF (17/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
FUNCTIONAL DESCRIPTION
The XA-SCC functions are described in the following sections.
Because all blocks are thoroughly documented in either the IC25 XA
Data Handbook, or the XA-SCC User Manual, only brief descriptions
are given in this datasheet, in conjunction with references to the
appropriate document.
XA CPU
The CPU is a 30MHz implementation of the standard XA CPU core.
See the XA Data Handbook (IC25) for details. The CPU core is
identical to the G3 core. See caveat in next paragraph about the Bus
Interface Unit.
Bus Interface Unit (BIU)
This is the internal Bus, not the bus at the pins. This internal bus
connects the CPU to the MIF (Memory and DRAM Controller.)
WARNING: Immediately after reset, always write BTRH = 51h,
followed by BTRL = 40h, in that order. Once written, do not change
the values in these registers. Follow these two writes with five
NOPS. Never write to the BCR register, it comes out of reset
initialized to 07h, which is the only value that will work.
Timers 0 and 1
Timers 0 and 1 are the standard XA-G3 timer 0 and 1. Each has an
associated I/O pin and interrupt. See the XA-G3 data sheet in the
IC25 XA Data Handbook for details. Many XA derivatives include a
standard XA Timer 2, and standard UARTs. These blocks have been
removed in order to provide other functions on the XA-SCC. There
is no Timer 2, and the UARTs have been replaced with full function
SCCs.
Watchdog Timer
This timer is a standard XA-G3 Watchdog Timer. See the G3
datasheet in IC25. Also, if you intend to use the Watchdog Timer to
assert the ResetOut pin, see ResetOut in the XA-SCC User Manual.
The Watchdog Timer is enabled at reset, and must be periodically
fed to prevent timeout. If the watchdog times out, it will generate an
internal reset; and if ResetOut is enabled the internal reset will
generate a ResetOut pulse (active low pulse on ResetOut pin.)
Reset
On the XA-SCC there are two pins associated with reset. The
ResetIn pin provides an external reset into the XA-SCC. The port
pin P3.2_Timer0_ResetOut output can be configured as ResetOut.
Because ResetOut does not reflect ResetIn, the ResetOut pin can
be tied directly back into the ResetIn pin without other PC board
logic. This configuration will make all resets (internal or external)
appear to the XA as external resets. See the XA-SCC User Manual
for a full discussion of the reset functions.
ResetIn
The ResetIn function is the standard XA-G3 ResetIn function. The
ResetIn signal does NOT get passed on to ResetOut. See the
XA-SCC User Manual for details on reset.
ResetOut
The P3.2_Timer0_ResetOut pin provides an external indication (if
the ResetOut function is enabled in the RSRSRC register) via an
active low output when an internal reset occurs (internal reset is
Reset instruction or Watchdog time out.) If the ResetOut function is
enabled, the ResetOut pin will be driven low when a Watchdog reset
occurs or the Reset instruction is executed. This signal may be used
to inform other devices in the system that the XA-SCC has been
internally reset. The ResetIn signal does NOT get passed on to
ResetOut. When activated, the duration of the ResetOut pulse is
256 system clocks.
WARNING: At power on time, from the time that power coming up is
valid, the P3.2_Timer0_ResetOut pin may be driven low for any
period from zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
Reset Source Register
The reset source identification register (RSTSRC) indicates the
cause of the most recent XA reset. The cause may have been an
externally applied reset signal, execution of the RESET instruction,
or a Watchdog reset. Figure 2 shows the fields in the RSTSRC
register. If the ResetOut function is tied back into the ResetIn pin,
then all resets will be external resets, and will thus appear as
external resets in the reset source register. RSTSRC[7] enables the
ResetOut function; 1 = Enabled, 0 = Disabled. See XA-SCC User
Manual for details; RSTSRC[7] differs in function from most other
XA derivatives.
EXTERNAL
MEMORY
and I/O BUS
XA CPU
BIU
INTERNAL CPU BUS
MIF and
DRAM
CONTROLLER
DMA
CHANNELS
x8
SU01123
Figure 2. XA CPU Core BIU (Bus Interface Unit)
1999 Mar 29
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