XA-SCC Datasheet, PDF (20/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
CS0
XA–SCC
CS1
CS2
OE
A19–A0
D15–D0
CS3
BLE
BHE
WE
CS
OE
A17–A9
D15–D0
A17–A8
A16–A0
D7–D0
RAS
CASL
CASH
OE
WE
A8–A0
D15–D0
RAS
CASL
CASH
OE
WE
A9–A0
D15–D0
RAS
CASL
CASH
WE
A15–A1
D15–D0
128K x 8 ROM
256K x 16 DRAM
(HM514260DI)
1M x 16 DRAM
(MT4C1M16C3)
32K x 16 SRAM
NOTE:
During DRAM cycles only, the appropriate CAS Address will be multiplexed onto pins A17–A7 after the assertion or RAS and prior to the assertion of BHE (CASH) and
BLE (CASL). See AC timing diagrams and the XA–SCC User Manual for complete details.
Figure 5. Typical System Bus Configuration
SU01126
1999 Mar 29
20