XA-SCC Datasheet, PDF (38/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
1
2
3
4
5
6
7
8
9
10
11
12
ClkOut
t_CHAV
A
t_CHAH
RAS ADDRESS
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
RAS
CASL
t_CHSL
t_AVSL
t_AVSL
t_CHSH
t_CHSL
t_CPWL
t_CPWH
t_CHSH
OE
D7–D0
NOTE 3
DRIVEN
BY XA
DRIVEN BY SLAVE
t_DIS
LS BYTE
NOTE 4
MS BYTE
LS BYTE
4 Byte Fetch is shown on 8 bit bus, burst can be 2 to 16 bytes.
NOTE 4: To meet hold time, EDO DRAM drives Data until OE rises, or until a new falling edge of CAS.
Data Bus is sampled on rising edge of clock 6, and every 2 clocks thereafter (clocks 6, 8, 10, and 12 in this example).
Figure 21. EDO DRAM Burst Code Fetch on 8 Bit Bus
t_CHSH
NOTE 4
MS BYTE
t_OHDE
SU01142
CLKOUT
A
RAS (CS)
CASL
WE
D[7:0]
t_CHAV
t_CHAV
RAS ADDRESS
t_CHSL
t_AVSL
t_CHSL
t_CHSL
t_CHAV
CAS ADDRESS (EVEN)
t_CHAH
t_CHAH
t_AVSL
t_CHAV
CAS ADDRESS (ODD)
t_CHAH
t_CHSH
t_CHSH
t_CPWH
t_DVSL
LS BYTE
t_DVSL
MS BYTE
Figure 22. DRAM 16 Bit Write on 8 Bit Bus (FPM or EDO DRAMs)
SU01143
1999 Mar 29
38