XA-SCC Datasheet, PDF (39/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
CLKOUT
RAS
CASH, CASL
t_CHSL
t_CLRL
t_CHSH
RAS and CAS terminate together. The active low portion of RAS can be programmed to last from 3 to 6 clock cycles.
The high portion of RAS after Refresh can be programmed to last from 2 to 4 clock cycles. See Chapter 3 of XA–SCC User Manual.
Figure 23. REFRESH
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t_RP
RAS
NOTE: t_RP min. is specified for each of the 5 individual RAS pins (CS_RAS[5:1]).
It is the minimum high time (thus RAS inactive) between two DRAM bus cycles on the same RAS pin.
Figure 24. RAS Precharge Time
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XTALIN
V_DD – 0.5
0.45 V
0.7 V_DD
0.2 V_DD – 0.1
t_CHCL
t_CLCX
t_CHCX
t_CLCH
t_C
Figure 25. External Clock Input Drive
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ClkOut
t_CODH
1999 Mar 29
WARNING: ClkOut is specified into 40 pF max, do not overload.
Figure 26. ClkOut Duty Cycle
39
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