XA-SCC Datasheet, PDF (18/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
RSTRC
Reg Type and Address = SFR 463h
Not Bit Addressable
Reset Value = see below
MSB
LSB
ROEN
—
—
—
—
R_WD R_CMD R_EXT
Bit:
7
6
5
4
3
2
1
0
Bit
Symbol
RSTSRC.7
RSTSRC.6
RSTSRC.5
RSTSRC.4
RSTSRC.3
RSTSRC.2
RSTSRC.1
RSTSRC.0
ROEN
–
–
–
–
R_WD
R_CMD
R_EXT
Function
ResetOut function enable bit – see XA–SCC User Manual for details
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Indicates that the last reset was caused by a watchdog timer overflow (see WARNING.)
Indicates that the last reset was caused by execution of the RESET instruction (see WARNING.)
Indicates that the last reset was caused by the external ResetIn input.
WARNING:
If ResetOut function is tied back into ResetIn pin, RSTSRC will always show external reset ONLY, because external reset always takes precedence over internal reset.
Figure 3. RSTSRC Reset Source Register
SU01124
DRAM Controller and Memory/IO Bus Interface
(MIF)
In the memory or system bus interface terminology, generic bus
cycles are synonymous with SRAM bus cycles, because these
cycles are designed to service SRAMs, Flash, EEPROM, peripheral
chips, etc. Chip select output pins function as either CS or RAS
depending on whether the memory bank has been programmed as
generic or DRAM.
The XA-SCC has a highly programmable memory bus interface with
a complete onboard DRAM controller. Most DRAMs (up to 8MBytes
per RAS pin), SRAMs, Flash, ROMs, and peripheral chips can be
connected to this interface with zero glue chips. The bus interface
provides 6 mappable chip select outputs, five of which can be
programmed to function as RAS strobes to DRAM. CAS generation,
proper address multiplexing for a wide range of DRAM sizes, and
refresh are all generated onboard. The bus timing for each individual
memory bank or peripheral can be programmed to accommodate
slow or fast devices.
Each memory bank and it’s associated RAS (chip select pin in
DRAM mode) output, can be programmed to access up to an
8MByte mappable address space in either EDO or FPM DRAM
modes (up to a total of 16MB of DRAM, or 32MB if 16MB of data
space and 16MB code space is elected. WARNING: Future
XA-SCC derivatives may not support separate code and data
spaces.)
Each memory bank and associated chip select programmed for
“generic” (SRAM, Flash, ROM, peripheral chips, etc) is capable of
supporting a 1Mbyte address space (six chip selects can thus
support 6MB of SRAM and other generic devices.)
The Memory Interface can be programmed to support both Intel
style and 68000 bus style SRAMs and peripherals.
1999 Mar 29
18