XA-SCC Datasheet, PDF (30/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
AC ELECTRICAL CHARACTERISTICS (3.3V "10%)
V_DD = 3.3V "10%, T_amb = –40_C to +85_C (industrial)
SYMBOL FIGURE
PARAMETER
LIMITS
MIN
MAX
UNIT
All Cycles
F_C
t_C
t_CHCX
t_CLCX
t_CLCH
t_CHCL
t_AVSL
t_CHAH
t_CHAV
t_CHSH
t_CHSL
t_CODH
25 System Clock (internally called CClk) Frequency
25 System Clock Period = 1/FC
25 XTALIN High Time
25 XTALIN Low Time
25 XTALIN Rise Time
25 XTALIN Fall Time
All Address Valid to Strobe low
All
Address hold after CLKOUT rising edge⁹
All Delay from CLKOUT rising edge to address valid
All
Delay from CLKOUT rising edge to Strobe High⁹
All
Delay from CLKOUT rising edge to Strobe Low⁹
26 ClkOut Duty Cycle High (into 40pF max.)
(See Warning Note 5 on page 31.)
0
33.33
t_C* 0.5
t_C* 0.4
–
–
t_C – 21
1
–
1
1
t_CHCX–7
30
–
–
–
5
5
–
–
30
28
25
t_CHCX+3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_CPWH
13, 14, 16, CAS Pulse Width High
20, 21, 22
t_C – 12
–
ns
t_CPWL
13, 21
All DRAM cycles
t_RP
24
CAS Pulse Width Low
RAS precharge time, thus minimum RAS high time⁸
t_C – 10
–
ns
(n * t_C) –16
–
ns
note 8
Generic Data Read Only
t_AHDR
9, 16 Address hold (A19–A1 only, not A0) after CS, BLE, BHE rise at end
t_C –12
–
ns
of Generic Data Read Cycle (not code fetch)
Data Read and Instruction Fetch Cycles
t_DIS
9, 10, Data In Valid setup to ClkOut rising edge
12–14, 16,
17, 20, 21
t_DIH
t_OHDE
Data In Valid hold after ClkOut rising edge²
10, 12, 13, OE high to XA Data Bus Driver Enable
16, 20, 21
32
–
ns
0
–
ns
t_C – 19
–
ns
Write Cycles
t_CHDV
t_DVSL
t_SHAH
t_SHDH
Refresh
11, 16
Clock High to Data Valid
Data Valid prior to Strobe Low
Minimum Address Hold Time after strobe goes inactive
Data hold after strobes (CS and BHE/BLE) high
–
30
ns
t_C – 23
–
ns
t_C – 25
–
ns
t_C – 25
–
ns
t_CLRL
Wait Input
21 CAS low to RAS low
t_C – 15
–
ns
t_WS
24 WAIT setup (stable high or low) prior to CLKOUT rising edge
25
–
ns
t_WH
24 WAIT hold (stable high or low) after CLKOUT rising edge
0
–
ns
NOTES:
1. On a 16 bit bus, if only one byte is being written, then only one of BLE_CASL or BHE_CASH will go active. On an 8 bit bus, BLE_CASL
goes active for all (odd or even address) accesses. BHE_CASH will not go active during any accesses on an 8 bit bus.
2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all generic reads and fetches, in order to
meet hold time, the slave device should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the
address changes. On all FPM DRAM reads and fetches, hold data valid on the bus until the earliest of RAS, CAS, or OE goes high
(inactive.) On all EDO DRAM reads and fetches, hold data valid on the bus until a new CAS is asserted, or until OE goes high (inactive.)
3. To avoid tri-state fights during read cycles and fetch cycles, do not drive data bus until OE goes active
1999 Mar 29
30