XA-SCC Datasheet, PDF (13/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
MMR Name
SCC3 Write Register 0
SCC3 Write Register 1
SCC3 Write Register 2
SCC3 Write Register 3
SCC3 Write Register 4
SCC3 Write Register 5
SCC3 Write Register 6
SCC3 Write Register 7
SCC3 Write Register 8
SCC3 Write Register 9
SCC3 Write Register 10
SCC3 Write Register 11
SCC3 Write Register 12
SCC3 Write Register 13
SCC3 Write Register 14
SCC3 Write Register 15
SCC3 Write Register 16
SCC3 Write Register 17
SCC3 Read Register 0
SCC3 Read Register 1
Reserved
SCC3 Read Register 3
SCC3 Read Register 6
SCC3 Read Register 7
SCC3 Read Register 8
Reserved
SCC3 Read Register 10
Reserved
DMA Control Register Ch.0 Rx
FIFO Control & Status Reg Ch.0 Rx
Segment Register Ch.0 Rx
Buffer Base Register Ch.0 Rx
Buffer Bound Register Ch.0 Rx
Address Pointer Reg Ch.0 Rx
Byte Count Register Ch.0 Rx
Data FIFO Register Ch.0 Lo Rx
Data FIFO Register Ch.0 Hi Rx
DMA Control Register Ch.1 Rx
FIFO Control & Status Register Ch.1 Rx
Segment Register Ch. 1 Rx
Buffer Base Register Ch. 1 Rx
Read/Write or
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Size
Address
Offset
Description
SCC3 Registers
8
8C0h Command register
8
8C2h Tx/Rx Interrupt & data transfer mode
8
8C4h Extended Features Control
8
8C6h Receive Parameter and Control
8
8C8h Tx/Rx misc. parameters & mode
8
8CAh Tx. parameter and control
8
8CCh Sync character or SDLC address field or Match
Character 0
8
8CEh Sync character or SDLC flag or Match Character 1
8
8D0h Transmit Data Buffer
8
8D2h Master Interrupt control
8
8D4h Misc. Tx/Rx control register
8
8D6h Clock Mode Control
8
8D8h Lower Byte of Baud rate time constant
8
8DAh Upper Byte of Baud rate time constant
8
8DCh Misc. Control bits
8
8DEh External/Status interrupt control
8
8E8h Match Character 2 (wr16)
8
8EAh Match Character 3 (wr17)
8
8E0h Tx/Rx buffer and external status
8
8E2h Receive condition status/residue code
8E4h
8
8E6h Interrupt Pending Register
8
8ECh SDLC byte count low register
8
8EEh SDLC byte count high & FIFO status
8
8F0h Receive Buffer
8F2h
8
8F4h Loop/clock status
8F6–8FEh
Rx DMA Registers
8
100h Control Register
8
101h Control & Status Register
8
102h Points to 64K data segment
8
104h Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
16
106h Upper Bound (plus 1) on A15–A0
16
108h Current Address pointer A15–A0
16
10Ah Corresponds to A15–A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
16
10Ch 10Ch = Byte 0 = older,
10Dh = Byte 1 = younger
16
10Eh 10Eh = Byte 2 = older,
10Fh = Byte 3 = younger
8
110h Control Register
8
111h Control & Status Register
8
112h Points to 64K data segment
8
114h Wrap Reload Value for A15 –A8, A7–A0 reloaded
to zero by hardware
Reset
Value
00h
xx
xx
00h
00h
00h
00h
xx
xx
xx
00h
xx
00h
00h
xx
f8h
00h
00h
—
—
—
—
—
—
—
—
—
—
00h
00h
00h
00h
0000h
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
00h
1999 Mar 29
13