XA-SCC Datasheet, PDF (35/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
CLKOUT
A
RAS (CS)
t_CHAV
t_CHAH
RAS ADDRESS
t_AVSL
t_CHSL
t_CHSL
CAS ADDRESS
t_CHSH
t_CHAH
CAS (BHE/BLE)
WE
D
t_CHDV
t_AVSL
NOTE 1
VALID DATA
t_CHSH
NOTE: If only one byte is being written, then only the corresponding CAS signal goes active. On 8 bit bus, CASH is inactive, and CASL goes active for
both even and odd addressed bytes.
: OE is inactive during all writes.
Figure 15. DRAM Write (on 16 Bit Bus, also 8 Bit Write on 8 Bit Bus)
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CLKOUT
A19–A1
A0
CS
t_CHAV
EVEN BYTE ADDRESS
t_AVSL
t_CHSL
ODD BYTE ADDRESS
t_CHAV
t_AHDR
t_CHSH
BLE
OE
NOTE 3
ÉÉÉÉÉÉÉÉÉÉ ^{D7–D0 DRIVEN BY XA}
t_DIS
On all cycles on 8 bit bus, BHE remains high (inactive).
NOTE 2
t_DIS
t_DIH
NOTE 2
t_OHDE
DRIVEN
BY XA
WARNING: On the external bus, ALL XA–SCC reads are 16 bit Reads. If the CPU instruction only specifies 8 bits, then the CPU uses the appropriate byte, and discards the extra
byte. Thus “8 Bit Reads” and “16 bit Reads” appear to be identical on the bus. On an 8 bit bus, this will appear as two consecutive 8 bit reads even though the CPU will only use one
of the two bytes.
WARNING: Some 8 bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and least expensive) solution is to
operate these 8 bit devices on a 16 bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this technique is that byte reads are faster
than on an 8 bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
Figure 16. Generic (SRAM, Flash, I/O Device, etc.) Read (16 Bit or 8 Bit) on 8 Bit Bus
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1999 Mar 29
35