XA-SCC Datasheet, PDF (37/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
CLKOUT
A
RAS
t_CHAV
t_CHAV
RAS ADDRESS
t_CHSL
t_CHAH
t_AVSL
CASL
(CASH STAYS HIGH)
OE
D[7:0]
t_CHSL
t_CHSL
t_AVSL
t_CHAV
CAS ADDRESS EVEN
t_CHAH
t_CHSH
t_CHAV
CAS ADDRESS ODD
t_CHAH
t_CHSH
t_DIS
LS BYTE
t_CPWH
t_DIH (NOTE 2)
NOTE 2
t_DIS
MS BYTE
Figure 19. 16 Bit Read on 8 Bit Bus, DRAM (both FPM and EDO)
SU01140
1
2
3
4
5
6
ClkOut
t_CHAV
A
RAS ADDR
t_CHAH
CAS ADDR
(EVEN)
RAS
t_CHSL
t_AVSL
t_CHSL
CASL
t_AVSL
7
8
9
CAS ADDR
(ODD)
t_CHSH
t_CPWH
10
11
12
13
14
15
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
t_CHSH
OE
D7–D0
t_DIS
LS BYTE
t_DIH (NOTE 2)
MS BYTE
LS BYTE
t_CHSH
t_DIH (NOTE 2)
MS BYTE
4 Byte Fetch is shown on 8 bit bus, burst can be 2 to 16 bytes.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 9, 12, and 15 in this example).
NOTE 2: If data is held valid on the bus until the earliest of CAS, RAS, or OE rises, then the hold time is met.
Figure 20. DRAM FPM (Fast Page Mode) Burst Code Fetch on 8 Bit Bus
t_OHDE
SU01141
1999 Mar 29
37