XA-SCC Datasheet, PDF (10/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
NAME
SWE
DESCRIPTION
Software Interrupt Enable
SFR
Address
47Ah
MSB
–
SWE7
BIT FUNCTIONS AND ADDRESSES
SWE6 SWE5 SWE4 SWE3
LSB
SWE2 SWE1
RESET
VALUE
00h
357
356
355
354
353
352
351
350
SWR*
Software Interrupt Request
42Ah
–
SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1
00h
TCON*
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control
Timer 0 High
Timer 1 High
Timer 0 Low
Timer 1 Low
Timer 0/1 Mode
287
286
285
284
283
282
281
280
410h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
451h
00h
453h
00h
450h
00h
452h
00h
45Ch
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00h
28F
28E
28D
28C
28B
28A
289
288
TSTAT* Timer 0/1 Extended Status
411h
–
–
–
–
–
T1OE
–
T0OE
00h
2FF
2FE
2FD
2FC
2FB
2FA
2F9
2F8
WDCON* Watchdog Control
41Fh
PRE2
PRE1
PRE0
–
–
WDRUN WDTOF
–
Note 8
WDL
Watchdog Timer Reload
45Fh
00h
WFEED1 Watchdog Feed 1
45Dh
xx
WFEED2 Watchdog Feed 2
45Eh
xx
NOTES:
* SFRs marked with an asterisk (*) are bit addressable.
# SFRs marked with a pound sign (#) are additional SFR registers specific to the XA-SCC.
1. The XA-SCC implements an 8-bit SFR bus, as stated in Chapter 8 of the IC25 Data Handbook XA User Guide. All SFR accesses must be
8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data
in the upper byte.
2. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future XA derivatives. The reset value shown for these bits is 0.
3. The XA guards writes to certain bits (typically interrupt flags) that may be written by a peripheral function. This prevents loss of an interrupt
or other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a
read-modify-write operation. XA-SCC SFR bits that are guarded in this manner are: TF1, TF0, IE1, and IE0 (in TCON), and WDTOF (in
WDCON).
4. Port configurations default to quasi-bidirectional when the XA begins execution after reset. Thus all PnCFGA registers will contain FFh
and PnCFGB register will contain 00h. See warning in XA-SCC User Manual about P3.2_Timer0_ResetOut pin during first 258 clocks after
power up. Basically, during this period, this pin may output a strongly driven low pulse. If the pulse does occur, it will terminate in a
transition to high at a time no later than the 259th system clock after valid VCC power up.
5. SFR is loaded from the reset vector.
6. F1, F0, and P reset to 0. All other bits are loaded from the reset vector.
7. The RSTSRC register reflects the cause of the last XA reset. One bit will be set to 1, the others will be 0. RSTSRC[7] enables the ResetOut
function; 1 = Enabled, 0 = Disabled. See XA-SCC User Manual for details; RSTSRC[7] differs in function from most other XA derivatives.
8. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.
1999 Mar 29
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