XA-SCC Datasheet, PDF (24/42 Pages) NXP Semiconductors – CMOS 16-bit communications microcontroller

Philips Semiconductors
CMOS 16-bit communications microcontroller
Preliminary specification
XA-SCC
PIN
IDL
FUNCTION
MUX
SCC 0
SCC 1
SCC 2
IDL On
IDL On
IF IDL ON
IDL PINS,
ELSE
SCC0 PINS
SCC1 PINS
OR GPIO
SCC2 PINS
OR GPIO
SCC 3
SCC3 PINS
OR GPIO
The Pin Function Mux is used to enable
alternate functions on unused pins.
Figure 7. IDL Connection Options
SU01128
Dual v.54 and 2047 Generators/Checkers
One of the two hardware generator/checkers which support the
V.54/2047 line testing standards can be attached to each SCC.
During V.54/2047 line testing sequences, the V.54/2047 units can be
programmed to generate an interrupt when certain error criteria
have been detected on the transmissions lines. The CPU can
determine the quality of the transmission line by reading the
V.54/2047 units’ status registers.
Autobaud Detectors
Each SCC has it’s own Autobaud detector, capable of baud rate
detection up to 921.6Kbaud. The detectors can be programmed to
automatically echo the industry standard autobaud sequences. They
can be programmed to update the necessary control registers in the
SCCs, and turn on the receiver; which in turn will automatically
initiate DMA into memory of received data. Thus, once the baud rate
is determined, reception begins without intervention from the
processor. When the baud rate is detected, a maskable interrupt is
sent to the processor. See the Autobaud chapter in the XA-SCC
User Manual for details.
I/O PORT OUTPUT CONFIGURATION
Port input/output configurations are the same as standard XA ports:
open drain, quasi-bidirectional, push-pull, and off (off means tri-state
Hi-Z, and allows the pin to be used as an input. WARNING: At
power on time, from the time that power coming up is valid, the
P3.2_Timer0_ResetOut pin may be driven low for any period from
zero nanoseconds up to 258 system clocks. This is true
independently of whether ResetIn is active or not.
POWER REDUCTION MODES
The XA-SCC supports Idle and Power Down modes of power
reduction. The idle mode leaves most peripherals running in order to
allow them to activate the processor when an interrupt is generated.
The power down mode stops the oscillator in order to absolutely
minimize power. The processor can be made to exit power down
mode via a reset or one of the external interrupt inputs (INT0 or
INT1). This will occur if the interrupt is enabled and its priority is
higher than that defined by IM3 through IM0. In power down mode,
the power supply voltage may be reduced to the RAM keep-alive
voltage V_RAM. This retains the RAM, register, and SFR contents at
the point where power down mode was entered. WARNING: V_DD
must be raised to within the operating range before power down
mode is exited.
INTERRUPTS
In the XA architecture, all exceptions, including Reset, are handled
in the same general exception structure. The highest priority
exception is of course Reset, and it is non-maskable. All exceptions
are vectored through the Exception Vector Table in low memory.
Coming out of Reset, these vectors must be stored in non-volatile
memory based at location 000000. Later in the boot sequence,
DRAM or SRAM can be mapped into this address space if desired.
There is a feature in the XA-SCC Memory Controller called “Bank
Swap” that supports replacing the ROM vector table and other low
memory with RAM. See the XA-SCC User Manual for details.
The XA-SCC has a standard XA CPU Interrupt Controller,
implemented with 15 Maskable Event Interrupts. Event Interrupts
are defined as maskable interrupts usually generated by hardware
events. However, in the XA-SCC, 4 of the 15 Event Interrupts are
generated by software writing directly to the interrupt flag bit. These
4 interrupts are referred to as High Priority Software Interrupts.
See the IC25 XA Data Handbook for a full explanation of the
exception structure, including event interrupts, of the XA CPU.
Because the High Priority Software Interrupts are specific to the
XA-SCC, they are explained in the XA-SCC User Manual.
1999 Mar 29
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