SAA7111A Datasheet, PDF (54/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
17.2.18 SUBADDRESS 13
Table 33 Output control 3 SA 13
FUNCTION
Bypass control LOW for VPO7 to VPO0
No bypass
Permanent bypass
Bypass controlled by V_GATE
Bypass controlled by delayed V_GATE
Bypass control HIGH for VPO15 to VPO8
No bypass
Permanent bypass
Bypass controlled by V_GATE
Bypass controlled by delayed V_GATE
Clock Reference Output Control
CREF is independent of VREF
CREF is LOW if VREF = 0
CREF is HIGH if VREF = 0
CREF always = 1
Vertical Reference Output Control (VREF)
Internal VREF
VREF_CCIR
Programmable V_GATE
Delayed programmable V_GATE
BIT NAME
BCLO1
BCLO0
BCLO1
BCLO0
BCLO1
BCLO0
BCLO1
BCLO0
BCHI1
BCHI0
BCHI1
BCHI0
BCHI1
BCHI0
BCHI1
BCHI0
CCTR1
CCTR0
CCTR1
CCTR0
CCTR1
CCTR0
CCTR1
CCTR0
VCTR1
VCTR0
VCTR1
VCTR0
VCTR1
VCTR0
VCTR1
VCTR0
LOGIC LEVEL CONTROL BIT
0
D1
0
D0
0
D1
1
D0
1
D1
0
D0
1
D1
1
D0
0
D3
0
D2
0
D3
1
D2
1
D3
0
D2
1
D3
1
D2
0
D5
0
D4
0
D5
1
D4
1
D5
0
D4
1
D5
1
D4
0
D7
0
D6
0
D7
1
D6
1
D7
0
D6
1
D7
1
D6
1998 May 15
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