SAA7111A Datasheet, PDF (31/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
handbook, full pagewidth
CVBS
VBI
burst
26 × 1/LLC
burst
179 × 1/LLC
processing delay CVBS->VPO⁽²⁾
Y - output
HREF (50 Hz)
RTS1 (PLIN)⁽¹⁾
HS
0
sync clipped
720 × 2/LLC
27 × 2/LLC
12 × 2/LLC
144 × 2/LLC
43 × 2/LLC
4/LLC
HS (50 Hz)
108
programming range
0
(step size: 8/LLC)
HREF (60 Hz)
23 × 2/LLC
HS (60 Hz)
720 × 2/LLC
16 × 2/LLC
138 × 2/LLC
−107
HS (60 Hz)
107
programming range
0
(step size: 8/LLC)
−106
MGD701
(1) PLIN is switched to output RTS1 via I²C-bus bit RTSE1 = 0.
(2) See Table 2.
(3) HDEL (1 : 0) = 0 0, YDEL (2 : 0) = 0 0 0.
Fig.23 Horizontal timing diagram.
1998 May 15
31