SAA7111A Datasheet, PDF (24/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
SYMBOL
PARAMETER
CONDITIONS
α_cs
channel crosstalk
f_i = 5 MHz
Analog-to-digital converters
B
φ_diff
G_diff
f_clkADC
DLE
ILE
bandwidth
differential phase
(amplifier plus anti-alias
filter = bypass)
differential gain
(amplifier plus anti-alias
filter = bypass)
ADC clock frequency
DC differential linearity
error
DC integral linearity error
at −3 dB
Digital inputs
V_IL(SCL,SDA)
V_IH
V_IL(xtal)
V_IH(xtal)
V_ILn
V_IHn
I_LI
C_i
C_i(n)
LOW level input voltage
pins SDA and SCL
HIGH level input voltage
pins SDA and SCL
LOW level CMOS input
voltage pin XTALI
HIGH level CMOS input
voltage pin XTALI
LOW level input voltage all
other inputs
HIGH level input voltage
all other inputs
input leakage current
input capacitance
outputs at 3-state
input capacitance all other
inputs
Digital outputs
V_OL(SCL,SDA)
V_OL
V_OH
V_OL(clk)
V_OH(clk)
I_LO
LOW level output voltage
pins SDA and SCL
LOW level output voltage
HIGH level output voltage
LOW level output voltage
for clocks
HIGH level output voltage
for clocks
output leakage current
SDA/SCL at 3 mA (6 mA)
sink current
V_DDD = max; I_OL = 2 mA
V_DDD = min, I_OH = −2 mA
at 3-state mode
FEI input timing
t_SU;DAT
t_HD;DAT
input data set-up time
input data hold time
MIN.
−
−
−
−
12.8
−
−
−0.5
0.7V_DDD
−0.3
2.0
−0.3
2.0
−
−
−
−
0
2.4
−0.5
2.4
−
13
3
TYP.
−
7
2
2
−
0.7
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1998 May 15
24
MAX.
−50
UNIT
dB
−
MHz
−
deg
−
%
14.3
MHz
−
LSB
−
LSB
+0.3V_DDD V
V_DDD + 0.5 V
+0.8
V
V_DDD + 0.3 V
+0.8
V
5.5
V
1
µA
8
pF
5
pF
0.4 (0.6) V
0.4
V
V_DDD + 0.5 V
+0.6
V
V_DDD + 0.5 V
10
µA
−
ns
−
ns