SAA7111A Datasheet, PDF (41/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
17 I²C-BUS DESCRIPTION
17.1 I²C-bus format
Table 7 Write procedure
S SLAVE ADDRESS W
ACK-s
SUBADDRESS
ACK-s DATA (N BYTES)
ACK-s P
Table 8 Read procedure (combined format)
S
SLAVE ADDRESS W
Sr
SLAVE ADDRESS R
ACK-s
ACK-s
SUBADDRESS
DATA (N BYTES)
ACK-s
ACK-m P
Table 9 Description of I²C-bus format
CODE
S
Sr
Slave address W
Slave address R
ACK-s
ACK-m
Subaddress
Data
P
X = LSB slave
address
Slave address
Subaddresses
DESCRIPTION
START condition
repeated START condition
0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)
0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)
acknowledge generated by the slave
acknowledge generated by the master
subaddress byte; see Table 10
data byte; see Table 10; note 1
STOP condition
read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)
read = 49H or 4BH; note 2
write = 48H or 4AH
IICSA = 0 or 1
00H chip version
read and write; note 3
01H reserved
−
02h to 05H front-end part
read and write
06H to 13H decoder part
14H reserved
15H to 17H decoder part
read and write
−
read and write
18H to 19H reserved
1AH to 1CH Line-21 text slicer part
1DH to 1EH reserved
1FH status byte
−
read only
−
read only
Notes
1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.
2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with
the I²C-bus specification).
3. The I²C-bus subaddress 00 has to be initialized with 0 before being read.
1998 May 15
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