SAA7111A Datasheet, PDF (32/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
handbook, full pagewidth
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input CVBS
HREF
VREF VRLN = 1⁽²⁾
VREF VRLN = 0⁽²⁾
VS
RTS0 (ODD)⁽¹⁾
535 x 2/LLC
(a) 1st field
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input CVBS
HREF
VREF VRLN = 1⁽²⁾
VREF VRLN = 0⁽²⁾
VS
RTS0 (ODD)⁽¹⁾
(b) 2nd field
77 x 2/LLC
MGG069
(1) ODD is switched to output RTS0 via I²C-bus bit RTSE0 = 0.
(2) Additional VREF positions can be achieved via I²C-bits VCTR1 and VCTR0 (see Fig.9).
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I²C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.24 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
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