SAA7111A Datasheet, PDF (53/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
17.2.17 SUBADDRESS 12
Table 32 Output control 2 SA 12, D7 to D6, D4 to D0
FUNCTION
Analog test select (AOSL)
AOUT connected to internal test point 1
AOUT connected to input AD1
AOUT connected to input AD2
AOUT connected to internal test point 2
Dithering (noise shaping) control (DIT)
Dithering off
Dithering on
RGB output format selection (RGB888)
RGB (5, 6 and 5)
RGB (8, 8 and 8)
Chrominance interpolation filter function (CBR)
Cubic interpolation (default)
Linear interpolation (lower bandwidth)
3-state control VPO7 to VPO0 (TCLO)
VPO7 to VPO0 depends on OEYC, FEI only (default)
(see Figs 18, 19 and 22)
VPO7 to VPO0 in 3-state [and OFTS (1 : 0) = 3]
(see Tables 3 and 6)
Real time outputs mode select (RTSE0)
ODD switched to output pin 40
VL switched to output pin 40
Real time outputs mode select (RTSE1)
PLIN switched to output pin 39
HL switched to output pin 39
BIT NAME
AOSL1
AOSL0
AOSL1
AOSL0
AOSL1
AOSL0
AOSL1
AOSL0
DIT
DIT
RGB888
RGB888
CBR
CBR
TCLO
TCLO
LOGIC LEVEL CONTROL BIT
0
D1
0
D0
0
D1
1
D0
1
D1
0
D0
1
D1
1
D0
0
D2
1
D2
0
D3
1
D3
0
D4
1
D4
0
D5
1
D5
RTSE0
0
D6
RTSE0
1
D6
RTSE1
0
D7
RTSE1
1
D7
1998 May 15
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