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SAA7111A Datasheet, PDF (25/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP
Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
SYMBOL
PARAMETER
CONDITIONS
Data and control output timing; note 1
CL
tOHD;DAT
tPD
tPDZ
output load capacitance
output hold time
propagation delay
propagation delay to
3-state
CL = 15 pF
CL = 25 pF
Clock output timing (LLC and LLC2); note 2
CL(LLC)
Tcy
output load capacitance
cycle time
LLC
LLC2
δLLC
duty factors for tLLCH/tLLC
and tLLC2H/tLLC2
CL = 25 pF
tr
rise time LLC, LLC2
tf
fall time LLC, LLC2
td
delay time LLC output to at 1.5 V;
LLC2 output
LLC/LLC2 = 25 pF
Data qualifier output timing (CREF)
tOHD;CREF
tPD;CREF
output hold time
propagation delay from
positive edge of LLC
CL = 15 pF
CL = 25 pF
Clock input timing (XTALI)
δXTALI
duty factor for tXTALIH/tXTALI nominal frequency
Horizontal PLL
fHn
nominal line frequency
50 Hz field
60 Hz field
∆fH/fHn
permissible static deviation
Subcarrier PLL
fSCn
nominal subcarrier
PAL BGHI
frequency
NTSC M; NTSC-Japan
PAL M
∆fSC
lock-in range
PAL N
Crystal oscillator
fn
nominal frequency
3rd harmonic; note 3
∆f/fn
permissible nominal
frequency deviation
MIN.
TYP.
MAX. UNIT
15
−
40
pF
4
−
−
ns
−
−
20
ns
−
−
20
ns
15
−
40
pF
35
−
39
ns
70
−
78
ns
40
−
60
%
−
−
5
ns
−
−
5
ns
−4
−
+8
ns
4
−
−
ns
−
−
20
ns
40
−
−
−
−
−
−
−
±400
−
−
−
60
15625 −
15734 −
−
5.7
4433619 −
3579545 −
3575612 −
3582056 −
−
−
24.576 −
−
±50
%
Hz
Hz
%
Hz
Hz
Hz
Hz
Hz
MHz
10−6
1998 May 15
25