SAA7111A Datasheet, PDF (35/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
14.2 Power-on control
Power-on reset is activated at power-on, chip enable, PLL clock generation failure and if the supply voltage falls below
2.7 V. The RES signal can be applied to reset other circuits of the digital picture processing system.
handbook, full pagewidth
CE
XTAL
LLCINT
RESINT
LLC
RES
CLOCK
PLL
LLC
CE
POC VDDA
ANALOG
POC VDDD
DIGITAL
POC
LOGIC
POC
DELAY
CLK0
RES
some ms
20 to 200 µs
PLL-delay
<1 ms
896 LCC
digital delay
128 LCC
CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock;
RESINT = internal reset; LLC = line-locked clock output; RES = reset output (active LOW).
Fig.27 Power-on control circuit.
1998 May 15
35
MGC633