SAA7111A Datasheet, PDF (37/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
Notes to Table 5
1. VPO bus allows connection to 5 V video data bus systems.
2. Values in accordance with CCIR 601.
3. Before and after the video data, video timing codes are inserted in accordance with CCIR 656.
a) VPO15 to VPO8 = VPO7 to VPO0 = CCIR 656 data if I²C-bus bit TCLO = 0
b) VPO15 to VPO8 = CCIR 656 data, VPO7 to VPO0 = 3-state if I²C-bus bit TCLO = 1.
4. During HREF = LOW RGB levels are set to 16 (10 hex). RGB 16-bit is achieved by dropping the LSBs of the 8-bit
signals (after dithering if desired).
5. CREF = 0 (see Fig.17).
6. CREF = 1 (see Fig.17).
+255
handbook, full pagewidth
+235
white
+255
+240
+212
blue 100%
blue 75%
+255
+240
+212
red 100%
red 75%
+128 LUMINANCE 100%
+128
colourless
U-COMPONENT
+128
colourless
V-COMPONENT
+16
black
0
a. Y output range.
+44
yellow 75%
+16
yellow 100%
0
b. U output range (Cb).
+44
cyan 75%
+16
cyan 100%
0
MGC634
c. V output range (Cr).
CCIR Rec. 602 digital levels.
Equations for modification to the YUV levels via BCS control I²C-bus bytes BRIG, CONT and SATN.
Luminance:
Y_OUT = Int ^{C-----O-7----1N-----T--} × (Y – 128) + BRIG
Chrominance:
UV_OUT = Int ^{S-----A-6---4T-----N--} × (Cr, Cb – 128) + 128
It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.
Fig.28 VPO output signal range with default BCS settings.
1998 May 15
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