SAA7111A Datasheet, PDF (47/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
17.2.7 SUBADDRESS 07
Table 19 Horizontal sync stop SA 07, D7 to D0
DELAY TIME
(STEP SIZE = 8/LLC)
−128...−108
−107...
...108 (50Hz)
...107 (60Hz)
109...127 (50Hz)
108...127 (60Hz)
HSS7
1
0
0
CONTROL BITS D7 to D0
HSS6 HSS5 HSS4 HSS3 HSS2 HSS1
forbidden (outside available central counter range)
0
0
1
0
1
0
1
1
0
1
1
0
1
1
0
1
0
1
forbidden (outside available central counter range)
HSS0
1
0
1
17.2.8 SUBADDRESS 08
Table 20 Sync control SA 08, D7 to D5, D3 to D0
FUNCTION
Vertical noise reduction (VNOI)
Normal mode
Searching mode
Free running mode
Vertical noise reduction bypassed
Horizontal PLL (HPLL)
PLL closed
PLL open, horizontal frequency fixed
TV/VTR mode select (VTRC)
TV mode
(recommended for poor quality TV signals only)
VTR mode (recommended as default setting)
Extended loop filter (EXFIL)
Word width of the loop filter (LF2) amplification = 16-bit
Word width of the loop filter (LF2) amplification = 14-bit
Field selection (FSEL)
50 Hz, 625 lines
60 Hz, 525 lines
Automatic field detection (AUFD)
Field state directly controlled via FSEL
Automatic field detection
BIT NAME LOGIC LEVEL CONTROL BIT
VNOI1
0
D1
VNOI0
0
D0
VNOI1
0
D1
VNOI0
1
D0
VNOI1
1
D1
VNOI0
0
D0
VNOI1
1
D1
VNOI0
1
D0
HPLL
0
D2
HPLL
1
D2
VTRC
0
D3
VTRC
1
D3
EXFIL
0
D5
EXFIL
1
D5
FSEL
0
D6
FSEL
1
D6
AUFD
0
D7
AUFD
1
D7
1998 May 15
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