SAA7111A Datasheet, PDF (43/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
17.2 I²C-bus detail
The I²C-bus receiver slave address is 48H/49H. Subaddresses 0F, 14, 18, 19, 1D and 1E are reserved; subaddress 01
is reserved for chip version.
17.2.1 SUBADDRESS 00
Table 11 Chip version SA00; note 1
FUNCTION
V1
Chip version
V2
Note
1. X = reserved.
ID07
0
0
ID06
0
0
ID05
0
1
LOGIC LEVELS
ID04
1
0
ID03
X
X
ID02
X
X
ID01
X
X
ID00
X
X
17.2.2 SUBADDRESS 02
Table 12 Analog control 1 SA02; note 1
FUNCTION⁽²⁾
Mode 0 : CVBS (automatic gain)
Mode 1 : CVBS (automatic gain)
Mode 2 : CVBS (automatic gain)
Mode 3 : CVBS (automatic gain)
Mode 4 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
Mode 5 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
Mode 6 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)
Mode 7 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)
CONTROL BITS D2 TO D0
MODE 2
0
0
0
0
1
1
1
1
MODE 1
0
0
1
1
0
0
1
1
MODE 0
0
1
0
1
0
1
0
1
Notes
1. Mode select (see Figs 33 to 40).
2. For modes 0 to 3 use BYPS(SA09,D7) = 0 (chrominance trap active), for modes 4 to 7 use BYPS = 1 (chrominance
trap bypassed).
Table 13 Analog control 1 SA 02, D5 to D3 (see Fig.14)
DECIMAL VALUE
0....
....7
UPDATE HYSTERESIS FOR 9-BIT GAIN
off
±7 LSB
CONTROL BITS D5 TO D3
GUDL 2
0
1
GUDL 1
0
1
GUDL 0
0
1
1998 May 15
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