SAA7111A Datasheet, PDF (36/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
Table 5 Power-on control sequence
INTERNAL POWER-ON CONTROL
SEQUENCE
PIN OUTPUT STATUS
FUNCTION
Directly after power-on
asynchronous reset
VPO15 to VPO0, RTCO, RTS0, RTS1,
GPSW, HREF, VREF, HS, VS, LLC,
LLC2 and CREF are in high-impedance
state
direct switching to high impedance for
20 to 200 ms
Synchronous reset sequence
LLC, LLC2, CREF, RTCO, RTS0,
RTS1, GPSW and SDA become active;
VPO15 to VPO0, HREF, VREF, HS and
VS are held in high-impedance state
internal reset sequence
Status after power-on control
sequence
VPO15 to VPO0, HREF, VREF, HS and after power-on (reset sequence) a
VS are held in high-impedance state complete I²C-bus transmission is
required
15 OUTPUT FORMATS
Table 6 Output formats of the VPO bus (note 1)
BUS
SIGNAL
VPO15
VPO14
VPO13
VPO12
VPO11
VPO10
VPO9
VPO8
VPO7
VPO6
VPO5
VPO4
VPO3
VPO2
VPO1
VPO0
Pixel
order Y
Pixel
order UV
Data rates
I²C-bus
control
signals
411 (12-BIT)
Y₀₇ Y₁₇ Y₂₇ Y₃₇
Y₀₆ Y₁₆ Y₂₆ Y₃₆
Y₀₅ Y₁₅ Y₂₅ Y₃₅
Y₀₄ Y₁₄ Y₂₄ Y₃₄
Y₀₃ Y₁₃ Y₂₃ Y₃₃
Y₀₂ Y₁₂ Y₂₂ Y₃₂
Y₀₁ Y₁₁ Y₂₁ Y₃₁
Y₀₀ Y₁₀ Y₂₀ Y₃₀
U₀₇ U₀₅ U₀₃ U₀₁
U₀₆ U₀₄ U₀₂ U₀₀
V₀₇ V₀₅ V₀₃ V₀₁
V₀₆ V₀₄ V₀₂ V₀₀
XXXX
XXXX
XXXX
XXXX
0123
0
LLC2
OFTS0 = 0
OFTS1 = 1
RGB888 = X
422
(16-BIT)⁽²⁾
Y₀₇
Y₁₇
Y₀₆
Y₁₆
Y₀₅
Y₁₅
Y₀₄
Y₁₄
Y₀₃
Y₁₃
Y₀₂
Y₁₂
Y₀₁
Y₁₁
Y₀₀
Y₁₀
U₀₇
V₀₇
U₀₆
V₀₆
U₀₅
V₀₅
U₀₄
V₀₄
U₀₃
V₀₃
U₀₂
V₀₂
U₀₁
V₀₁
U₀₀
V₀₀
0
1
0
LLC2
OFTS0 = 1
OFTS1 = 0
RGB888 = X
CCIR-656 (8-BIT)⁽³⁾ RGB (16-BIT)⁽⁴⁾
U₀₇ Y₀₇ V₀₇ Y₁₇
R4
U₀₆ Y₀₆ V₀₆ Y₁₆
R3
U₀₅ Y₀₅ V₀₅ Y₁₅
R2
U₀₄ Y₀₄ V₀₄ Y₁₄
R1
U₀₃ Y₀₃ V₀₃ Y₁₃
R0
U₀₂ Y₀₂ V₀₂ Y₁₂
G5
U₀₁ Y₀₁ V₀₁ Y₁₁
G4
U₀₀ Y₀₀ V₀₀ Y₁₀
G3
XXXX
G2
XXXX
G1
XXXX
G0
XXXX
B4
XXXX
B3
XXXX
B2
XXXX
B1
XXXX
B0
0
1
−
0
−
LLC
OFTS0 = 1
OFTS1 = 1
RGB888 = X
LLC2
OFTS0 = 0
OFTS1 = 0
RGB888 = 0
RGB (24-BIT)⁽⁴⁾
R7
R6
R5
R4
R3
G7
G6
G5
G4
G3
G2
B7
B6
B5
B4
B3
note 5
R7
R6
R5
R4
R3
G7
G6
G5
R2
R1
R0
G1
G0
B2
B1
B0
note 6
−
−
OFTS0 = 0
OFTS1 = 0
RGB888 = 1
1998 May 15
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