SAA7111A Datasheet, PDF (17/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
handbook, full pagewidth
TBP7 to 0
(CVBS)
Y or YUV
BCHI1 to 0
I²C-bus
UV or YUV
BCLO1 to 0
I²C-bus
0
MUX
CVBS
UP
1
SWHI
AD1BYP
(LUMA see Fig. 37)
0
MUX
BYP
UP
1
VBP0
VBP4
BCHI1
0
0
1
1
BCHI0
0
1
0
1
SWHI
1
0
VBP0
VBP4
REGISTER
0
MUX
CVBS
UP
1
SWLO
AD2BYP
(CHROMA see Fig. 37)
0
MUX
BYP
UP
1
VBP0
VBP4
BCLO1 BCLO0 SWLO
0
0
1
0
1
0
1
0
VBP0
1
1
VBP4
REGISTER
VPO15 to 8
VIPB
I²C-bus
VPO7 to 0
V_GATE
(programmable)
HREFINT
REG
EN
CLOCK 0
4 × REG
CLOCK 0
VBP4
VBP0
MGG064
HREFINT = internal horizontal reference.
TBP = upsampled CVBS input data (27 MHz).
AD1BYP/AD2BYP = digitized CVBS input data and Y/C input data (13.5 MHz).
VBP0 = programmable vertical reference signal.
VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).
Fig.8 Multiplexing of the CVBS signal to the VPO-bus.
1998 May 15
17