SAA7111A Datasheet, PDF (29/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
handbook, full pagewidth LLC
CREF
HREF
FEI
VPO
tSU;DAT
tHD;DAT
tPDZ
tOHD;DAT
tPD
to 3-state
from 3-state
MGC657
Timing is compatible with SAA7110; I²C-bus bit FECO = 0.
Fig.19 FEI timing diagram (FEI sampling at CREF = LOW) for OFTS = 0, 1 or 2).
handbook, full pagewidth
HIGH
128
BIT NO.:
LOW
15
transmitted once per line
SEQUENCE
INCRHPLL
16
2
INCRFSCPLL
45
DTO RESET⁽¹⁾
RESERVED
50 Hz fields: 235
60 Hz fields: 232
31
0 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIME SLOT: 0 1
16 19
63 67 68
MGC649
(1) Set to zero for one transmission, if a phase reset of the f_sc − DTO is applied via I²C-bus bit CDTO. RTCO sequence is generated in LLC/4.
The HPLL increment represents the actual LFCO frequency (f_LFCO × 4 = f_LLC); 16 LSB from 20, upper four bits are fixed to 0100b.
f_LFCO = ^{I---N--2--C--}_w---_o^R--_r--_d-^H---_lP-_e--_n-^L--_g-^L-_t-_h--^×--_D--f-_T-^X--_O--^T-₂--^A---^L-
Where: f_XTAL = 24.576 MHz, word length DTO2 = 20 bits.
The f_sc increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.
f_sc = ^{I---N----C-2----}_w^R---_o--^Fr--_d-^S---_lC-_e--_n-^P--_g-^L-_t-_h-^L---_D-^×--_T---f_O--^X--₁-^T---^A---^L- × -I--N----C---2--R--₁---_9H---^P----^L---^L
Where: word length DTO1 = 24 bits.
Fig.20 Real time control output.
1998 May 15
29