SAA7111A Datasheet, PDF (10/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
8 FUNCTIONAL DESCRIPTION
8.1 Analog input processing
The SAA7111A offers four analog signal inputs, two
analog main channels with source switch, clamp circuit,
analog amplifier, anti-alias filter and video CMOS ADC
(see Fig.5).
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.
8.2 Analog control circuits
The anti-alias filters are adapted to the line-locked clock
frequency via a filter control circuit. During the vertical
blanking time, gain and clamping control are frozen.
8.2.1 CLAMPING
The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.
handbook, halfpage
255
TV line
analog line blanking
GAIN CLAMP
60
1
HCL
HSY
MGL065
Fig.3 Analog line with clamp (HCL) and gain
range (HSY).
8.2.2 GAIN CONTROL
Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 13 and 14) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.
The gain control circuit receives (via the I²C-bus) the static
gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain
control (AGC) as part of the Analog Input Control (AICO).
handbook, halfpage
analog input level
maximum
+4.5 dB
0 dB
(1 V(p-p) 27/47 Ω)
−7.5 dB
range tbf
minimum
controlled
ADC input level
0 dB
MGG063
Fig.4 Automatic gain range.
8.3 Chrominance processing
The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90° phase relationship to the demodulator axis).
The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals (PAL and NTSC) or the 0 and 90° FM-signals
(SECAM).
The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions:
• AGC (Automatic Gain Control for chrominance
PAL and NTSC)
• Chrominance amplitude matching (different gain factors
for R − Y and B − Y to achieve CCIR-601 levels
Cr and Cb for all standards)
• Chrominance saturation control
• Luminance contrast and brightness
• Limiting YUV to the values 1 (min.) and 254 (max.) to
fulfil CCIR-601 requirements.
1998 May 15
10