SAA7111A Datasheet, PDF (27/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
13 TIMING DIAGRAMS
Product specification
SAA7111A
handbook, full pagewidth
CLOCK OUTPUT LLC
OUTPUTS VPO, HREF,
VREF, VS, HS
tLLC
tLLCL
tf
tLLCH
tPD
tOHD;DAT
2.6 V
1.5 V
0.6 V
tr
2.4 V
0.6 V
MGC658
An explanation of the output formats is given in Table 6.
Fig.15 Clock/data timing (8-bit CCIR-656 format of the VPO-bus).
handbook, full pagewidth
CLOCK OUTPUT LLC
OUTPUT CREF
CLOCK OUTPUT LLC2
OUTPUTS VPO, HREF,
VREF, VS, HS
tLLC
tLLCL
tLLCH
tf
tPD
tLLC
tr
tPD
tOHD;CREF
tdLLC2
tOHD;CREF
tPD
tOHD;DAT
2.6 V
1.5 V
0.6 V
2.4 V
0.6 V
tdLLC2
2.6 V
1.5 V
0.6 V
2.4 V
0.6 V
MGC659
An explanation of the output formats is given in Table 6. The FEI timing of the VPO-bus is illustrated in Figs 18 and 19.
Fig.16 Clock/data timing (12 and 16-bit CCIR-601 format of the VPO-bus).
1998 May 15
27