SAA7111A Datasheet, PDF (18/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
handbook, full pagewidth
VREF CCIR 656
HREFINT
VBP0
VBP4
VREFINT
HREFINT
REG
EN
CLOCK 0
REG
EN
CLOCK 0
VV
CC
TT
RR
10
VREFOUT
0 0 VREFINT
0 1 VREF CCIR 656
1 0 VBP0
1 1 VBP4
VCTR1 to 0
VREF_CCIR 656 = vertical reference signal referring to the field interval definitions of CCIR656.
HREFINT = internal horizontal reference signal.
VREFINT = internal vertical reference signal.
VBP0 = programmable vertical reference signal.
VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).
Fig.9 VREF output signal generation.
REG
HREF
0
MUX
1
COMPO
CLK0
REG
VREF
CLOCK 0
MGG065
handbook, full pagewidth
CREFINT
selected
VREF
CCTR1 to 0
CC
CC
TT
RR
10
CREFOUT
0 0 CREFINT
0 1 0 if VREF = 0
1 0 1 if VREF = 0
1 1 1 (always HIGH)
REG
CREF
CLOCK 0
MGG066
CREFINT = internal clock qualifier signal.
Fig.10 CREF output signal generation.
1998 May 15
18