SAA7111A Datasheet, PDF (34/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
Table 3 Digital output control
OEYC
0
1
0
1
0
1
0
1
FEI
TCLO⁽¹⁾
VPO
15 to 8
VPO
7 to 0
0
0
Z
0
0
active
1
0
Z
1
0
Z
0
1
Z
Z
0
1
active
Z
1
1
Z
Z
1
1
Z
Z
Note
1. Only active in 656-format (OFTS = 3).
14 CLOCK SYSTEM
14.1 Clock generation circuit
The internal CGC generates the system clocks LLC, LLC2
and the clock reference signal CREF. The internally
generated LFCO (triangular waveform) is multiplied by 4
via the analog PLL (including phase detector, loop filter,
VCO and frequency divider). The rectangular output
signals have a 50% duty factor.
Table 4 Clock frequencies
CLOCK
XTAL
LLC
LLC2
LLC4
LLC8
FREQUENCY (MHz)
24.576
27
13.5
6.75
3.375
handbook, full pagewidth
LFCO
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
LOOP
FILTER
OSCILLATOR
LLC
DIVIDER
1/2
DIVIDER
1/2
LLC2
DELAY
MGC632
CREF
Fig.26 Block diagram of clock generation circuit.
1998 May 15
34