SAA7111A Datasheet, PDF (33/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
handbook, full pagewidth
input CVBS
522 523 524 525 1
2
3
4
5
6
7
8
17 18 19
(525) (1)
(2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (20) (21) (22)
(2)
HREF
VREF
VREF
VRLN = 1⁽³⁾
VRLN = 0⁽³⁾
VS
RTS0 (ODD)⁽¹⁾
(a) 1st field
520 x 2/LLC
input CVBS
259 260 261 262 263 264 265 266 267 268 269 270 271 280 281 282
(262) (263) (264) (265) (266) (267) (268) (269) (270) (271) (272) (273) (274) (283) (284) (285)
(2)
HREF
VREF
VREF
VRLN = 1⁽³⁾
VRLN = 0⁽³⁾
VS
RTS0 (ODD)⁽¹⁾
(b) 2nd field
81 x 2/LLC
MGG070
(1) ODD is switched to output RTS0 via I²C-bus bit RTSE0 = 0.
(2) Line numbers in parenthesis refer to CCIR line counting.
(3) Additional VREF positions can be achieved via I²C-bus bits VCTR1 and VCTR0 (see Fig.9).
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I²C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.25 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
33