SAA7111A Datasheet, PDF (50/72 Pages) NXP Semiconductors – Enhanced Video Input Processor EVIP

Philips Semiconductors
Enhanced Video Input Processor (EVIP)
Product specification
SAA7111A
17.2.14 SUBADDRESS 0E
Table 26 Chrominance control SA 0E
FUNCTION
BIT NAME
LOGIC
LEVEL
Chroma bandwidth (CHBW0 and CHBW1)
Small bandwidth (≈ 620 kHz)
Nominal bandwidth (≈ 800 kHz)
Medium bandwidth (≈ 920 kHz)
Wide bandwidth (≈ 1000 kHz)
CHBW1
0
CHBW0
0
CHBW1
0
CHBW0
1
CHBW1
1
CHBW0
0
CHBW1
1
CHBW0
1
Fast colour time constant (FCTC)
Nominal time constant
Fast time constant
FCTC
0
FCTC
1
Disable chrominance comb filter (DCCF)
Chrominance comb filter on (during VREF = 1) (see Figs 24 and 25)
DCCF
0
Chrominance comb filter off
DCCF
1
Colour standard (CSTD0 to CSTD2); logic levels 100, 110 and 111 are reserved, do not use
Colour standard control automatic switching between PAL BGHI and
CSTD2
0
NTSC M (NTSC-Japan with special level adjustment; luminance
CSTD1
0
brightness subaddress 0A = 95H, luminance contrast
subaddress 0BH = 48H)
CSTD0
0
Colour standard control automatic switching between NTSC 4.43 (50 Hz) CSTD2
0
and PAL 4.43 (60 Hz)
CSTD1
0
CSTD0
1
Colour standard control automatic switching between PAL N and
NTSC 4.43 (60 Hz)
CSTD2
0
CSTD1
1
CSTD0
0
Colour standard control automatic switching between NTSC N and
PAL M
CSTD2
0
CSTD1
1
CSTD0
1
Colour standard control automatic switching between SECAM and
PAL 4.43 (60 Hz)
CSTD2
1
CSTD1
0
CSTD0
1
Clear DTO (CDTO)
Disabled
CDTO
0
Every time CDTO is set, the internal subcarrier DTO phase is reset to 0°
CDTO
1
and the RTCO output generates a logic 0 at time slot 68 (see RTCO
description Fig.20). So an identical subcarrier phase can be generated by
an external device (e.g. an encoder).
CONTROL
BIT
D1
D0
D1
D0
D1
D0
D1
D0
D2
D2
D3
D3
D6
D5
D4
D6
D5
D4
D6
D5
D4
D6
D5
D4
D6
D5
D4
D7
D7
1998 May 15
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