NS32FX16-15 Datasheet, PDF (9/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

2 0 Architectural Description (Continued)
I If Ie1 then all interrupts will be accepted If Ie0 only
the NMI interrupt is accepted Trap enables are not af-
fected by this bit
B Reserved for use by the CPU This bit is set to 1 during
the execution of the EXTBLT instruction and causes the
BPU signal to become active Upon reset B is set to
zero and the BPU signal is set high
Note 1 When an interrupt is acknowledged the B I P S and U bits are set
to zero and the BPU signal is set high A return from interrupt will
restore the original values from the copy of the PSR register saved
in the interrupt stack
Note 2 If BITBLT (BB) or EXTBLT instructions are executed in an interrupt
routine the PSR bits J and K must be cleared first
2 1 4 Configuration Register
The Configuration Register (CFG) is 8 bits wide of which
four bits are implemented The implemented bits are used to
declare the presence of certain external devices and to se-
lect the clock scaling factor CFG is programmed by the
SETCFG instruction The format of CFG is shown in Figure
2-3 The various control bits are described below
7
0
CMF I
FIGURE 2-3 Configuration Register (CFG)
I Interrupt vectoring This bit controls whether maskable
interrupts are handled in nonvectored (Ie0) or vectored
(Ie1) mode Refer to Section 3 2 3 for more information
F Floating-point instruction set This bit indicates whether
a floating-point unit (FPU) is present to execute floating-
point instructions If this bit is 0 when the CPU executes
a floating-point instruction a Trap (UND) occurs If this
bit is 1 then the CPU transfers the instruction and any
necessary operands to the FPU using the slave-proces-
sor protocol described in Section 3 1 3 1
M Clock scaling This bit is used in conjuction with the C bit
to select the clock scaling factor
C Clock scaling Same as the M bit above Refer to Sec-
tion 3 5 3 on ‘‘Power Save Mode’’ for details
2 1 5 DSP Module Registers
The DSP Module (DSPM) contains 6 memory-mapped reg-
isters All the registers except ST are readable and writa-
ble ST is read-only
Accesses to these registers must be aligned word and dou-
ble-word accesses must occur on word and double-word
address boundaries respectively Section 2 2 Failing to do
so will cause unpredictable results Figure 2-4 shows the
address map of the DSP Module Registers
Register Names
Register
Addresses
A
FFFFD400
Y
FFFFD404
0
DPTR
FFFFD408
CPTR
FFFFD40C
CTL FFFFD40E
ST FFFFD410
FIGURE 2-4 DSP Module Registers Address Map
A Accumulator This 32-bit register holds one complex
number and is mapped into two consecutive 16-bit words
called A0 and A1
Internally A0 and A1 are 32-bit registers however only bits
15 – 30 (16 bits) are accessible The rest of the bits are used
for bigger dynamic range during intermediate calculations
Section 3 4
Y Multiplier Input Register This 32-bit register holds one
complex operand The Y register is mapped into two con-
secutive words called Y0 and Y1
DPTR Data Pointer 24-bit pointer pointing at the data
vector in main memory In order to implement circular buff-
ers only the least significant bits of DPTR are incremented
When the end of a buffer is reached the least significant
bits of DPTR are reloaded with zeros The number of bits
that are set to zero (which defines the size of the circular
buffer) is controlled by the CTL register The least-signifi-
cant 16-bit word of DPTR is called DPTR0 and the most-
significant byte is called DPTR1 Bits 24 – 31 are reserved
and should be set to 0
CPTR Coefficient Memory Vector Pointer This 16-bit
register holds the address and length of the coefficient vec-
tor stored in the on-chip RAM array The format of CPTR is
shown in Figure 2–5
15 14 8 7 6
0
0 LNGT 0 STRT
FIGURE 2-5 CPTR Register Format
STRT Coefficient’s Vector Index At the beginning of the
DSP operation STRT points to the first coefficient in
the coefficient vector Section 2 1 6
LNGT Coefficient’s Vector Length This field specifies the
number of coefficients in the coefficient vector
STRT and LNGT must be in the ranges 0 to 95 and 1 to 96
respectively The relation LNGT a STRT ^k97 must also be
satisfied Specifying values violating any of these conditions
will cause unpredictable results
CTL Control Register This register controls the modes of
operation of the DSP Module The format of CTL is shown in
Figure 2-6 The reserved bits should be set to 0 See Sec-
tion 3 4 for more details
7 65 43 21 0
OPC DS RES OPM
FIGURE 2-6 CTL Register Format
OPM Opcode Modifier This field is used to further qualify
the operation specified by OPC See Section 3 4 3 for
details
DS Data Buffer Size Specifies the number of complex
variables (4 bytes each) in the data buffer in main
memory
x DS e 00 8 Complex Variables
x DS e 01 16 Complex Variables
x DS e 10 32 Complex Variables
x DS e 11 64 Complex Variables
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