NS32FX16-15 Datasheet, PDF (2/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

Table of Contents
1 0 PRODUCT INTRODUCTION
1 1 NS32FX16 Special Features
2 0 ARCHITECTURAL DESCRIPTION
2 1 Register Set
2 1 1 General Purpose Registers
2 1 2 Address Registers
2 1 3 Processor Status Register
2 1 4 Configuration Register
2 1 5 DSP Module Registers
2 1 6 RAM Array
2 2 Memory Organization
2 2 1 Address Mapping
2 3 Modular Software Support
2 4 Instruction Set
2 4 1 General Instruction Format
2 4 2 Addressing Modes
2 4 3 Instruction Set Summary
2 4 Graphic Support
2 5 1 Frame Buffer Addressing
2 5 2 BITBLT Fundamentals
2 5 2 1 Frame Buffer Architecture
2 5 2 2 BIT Alignment
2 5 2 3 Block Boundaries and Destination
Masks
2 5 2 4 BITBLT Directions
2 5 2 5 BITBLT Variations
2 5 3 Graphics Support Instructions
2 5 3 1 BITBLT (BIT-aligned BLock Transfer)
2 5 3 2 Pattern Fill
2 5 3 3 Data Compression Expansion and
Magnify
2 5 3 3 1 Magnifying Compressed Data
3 0 FUNCTIONAL DESCRIPTION
3 1 Instruction Execution
3 1 1 Operating States
3 1 2 Instruction Endings
3 1 2 1 Completed Instructions
3 1 2 2 Suspended Instructions
3 1 2 3 Terminated Instructions
3 1 2 3 Partially Completed Instructions
3 1 3 Slave Processor Instructions
3 1 3 1 Slave Processor Protocol
3 1 3 2 Floating-Point Instructions
3 2 Exception Processing
3 2 1 Exception Acknowledge Sequence
3 2 2 Returning from an Exception Service Procedure
3 2 3 Maskable Interrupts
3 2 3 1 Non-Vectored Mode
3 2 3 2 Vectored Mode Non-Cascaded Case
3 2 3 3 Vectored Mode Cascaded Case
3 2 4 Non-Maskable Interrupt
3 2 5 Traps
3 2 6 Priority among Exceptions
3 2 7 Exception Acknowledge Sequences Detailed
Flow
3 2 7 1 Maskable Non-Maskable Interrupt
Sequence
3 2 7 2 SLAVE ILL SVC DVZ FLG BPT UND
Trap Sequence
3 2 7 3 Trace Trap Sequence
3 3 Debugging Support
3 3 1 Instruction Tracing
3 4 DSP Module (DSPM)
3 4 1 DSPM Operation
3 4 2 Complex Number Representation
3 4 3 DSPM Instructions
3 4 4 Circular Buffers
3 5 System Interface
3 5 1 Power and Grounding
3 5 2 Clocking
3 5 3 Power Save Mode
3 5 4 Resetting
3 5 5 Bus Cycles
3 5 5 1 Bus Status
3 5 5 2 Basic Read and Write Cycles
3 5 5 3 Cycle Extension
3 5 5 4 Instruction Fetch Cycles
3 5 5 5 Interrupt Control Cycles
3 5 5 6 Special Bus Cycles
3 5 5 7 Slave Processor Bus Cycles
3 5 5 8 Data Access Sequences
3 5 5 9 Bus Access Control
3 5 5 10 Instruction Status
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