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NS32FX16-15 Datasheet, PDF (63/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor
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4 0 Device Specifications (Continued)
4 4 2 Timing Tables (Continued)
4 4 2 1 Output Signals Internal Propagation Delays NS32FX16-15 NS32FX16-20 NS32FX16-25
Symbol Figure
Description
Reference
Conditions
NS32FX16-15
Min
Max
NS32FX16-20
Min
Max
NS32FX16-25
Min
Max
Units
tIASa
tIASia
4-6 IAS Signal Active
4-6 IAS Signal Inactive
(Note 4)
After R E CTTL T1
14
13
12
ns
After R E CTTL T1 0 5 tCTp 0 5 tCTp 0 5 tCTp 0 5 tCTp 0 5 tCTp 0 5 tCTp
b6 ns a16 ns b6 ns a15 ns b6 ns a14 ns
tIASw
4-6 IAS Pulse Width
At 0 8V (Both Edges) 20
15
10
ns
tAIASs
4-6 AD0–AD15 Setup Before IAS T E
10
10
10
ns
tILOa
4-14 ILO Signal Active
After R E CTTL
14
13
12
ns
tILOia
4-14 ILO Signal Inactive After R E CTTL
14
13
12
ns
tRSTOa 4-19 RSTO Signal Active After R E CTTL
14
13
12
ns
tRSTOia 4-19 RSTO Signal Inactive After R E CTTL
14
13
12
ns
tRTOI
4-19 Reset to Idle
After F E of RSTO
10
(Note 3)
10
10
tCTp
Note 1 Every memory cycle starts with T4 during which Cycle Status is applied If the CPU was idling the sequence will be ‘‘ Ti T4 T1 ’’ If the CPU was
not idling the sequence will be ‘‘ T4 T1 ’’
Note 2 The parameters related to the ‘‘floating not floating’’ conditions are guaranteed by characterization Due to tester conditions these parameters are not
100% tested
Note 3 Not tested guaranteed by design
Note 4 Minimum values not tested guaranteed by design
Note 5 When the load on AD0–15 is increased to 90 pF the value of tALv is increased by no more than 5 ns When the load on A16–23 is increased to 90 pF the
value of tAHv is increased by no more than 5 ns
4 4 2 2 Input Signal Requirements NS32FX16-15 NS32FX16-20 and NS32FX16-25
Symbol Figure
Description
Reference
Conditions
NS32FX16-15
Min Max
tXp
4-15 OSCIN Clock Period R E OSCIN
to Next R E OSCIN
33
500
tXh
4-15 OSCIN High Time
At 4 2V (Both Edges) 0 5 tXp
(External Clock)
b 5 ns
tXI
4-15 OSCIN Low Time
At 1 0V (Both Edges) 0 5 tXp
b 5 ns
tDIs
4-4 4-11 Data In Setup
tDIh
4-4 4-11 Data In Hold
(Note 1)
Before R E CTTL T4 15
After R E CTTL T4
2
tCWs
4-4 4-5 CWAIT Signal Setup Before R E CTTL
22
T3 or T3(w)
tCWh
4-4 4-5 CWAIT Signal Hold After R E CTTL
2
T3 or T3(w)
tWs
4-4 4-5 WAITn Signals Setup Before R E CTTL
22
T3 or T3(w)
tWh
4-4 4-5 WAITn Signals Hold After R E CTTL
2
T3 or T3(w)
tHLDs 4-7 4-8 HOLD Setup Time Before R E CTTL
16
T2 or Ti
tHLDh 4-7 4-8 HOLD Hold Time
After R E CTTL Ti
2
NS32FX16-20
Min Max
25
500
0 5 tXp
b 4 ns
0 5 tXp
b 4 ns
14
2
18
2
21
2
15
2
NS32FX16-25
Min Max
20
500
0 5 tXp
b 3 ns
0 5 tXp
b 3 ns
10
2
10
2
20
2
14
2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
63
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