NS32FX16-15 Datasheet, PDF (12/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

2 0 Architectural Description (Continued)
Note Dashed lines indicate information copied to register during transfer of control between modules
FIGURE 2-10 NS32FX16 Run-Time Environment
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2 4 INSTRUCTION SET
2 4 1 General Instruction Format
Figure 2-11 shows the general format of a Series 32000
instruction The Basic Instruction is one to three bytes long
and contains the Opcode and up to two 5-bit General Ad-
dressing Mode (‘‘Gen’’) fields Following the Basic Instruc-
tion field is a set of optional extensions which may appear
depending on the instruction and the addressing modes se-
lected
Index Bytes appear when either or both Gen fields specify
Scaled Index In this case the Gen field specifies only the
Scale Factor (1 2 4 or 8) and the Index Byte specifies
which General Purpose Register to use as the index and
which addressing mode calculation to perform before index-
ing
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the select-
ed addressing modes Each Disp lmm field may contain
one of two displacements or one immediate value The size
of a Displacement field is encoded within the top bits of that
field as shown in Figure 2-13 with the remaining bits inter-
preted as a signed (two’s complement) value The size of an
immediate value is determined from the Opcode field Both
Displacement and Immediate fields are stored most-signifi-
cant byte first Note that this is different from the memory
representation of data (Section 2 2)
Some instructions require additional ‘‘implied’’ immediates
and or displacements apart from those associated with ad-
dressing modes Any such extensions appear at the end of
the instruction in the order that they appear within the list of
operands in the instruction definition (Section 2 4 3)
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FIGURE 2-12 Index Byte Format
FIGURE 2-11 General Instruction Format
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