NS32FX16-15 Datasheet, PDF (52/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

3 0 Functional Description (Continued)
TL EE 10818–33
FIGURE 3-27 NS32FX16 and FPU Interconnections
TL EE 10818 – 36
FIGURE 3-28 Memory Interface
TABLE 3-7 Bus Cycle Categories
Category
HBE
A0
Even Byte
1
0
Odd Byte
0
1
Even Word
0
0
Accesses of operands requiring more than one bus cycle
are performed sequentially with no idle T-states separating
them The number of bus cycles required to transfer an op-
erand depends on its size and its alignment (i e whether it
starts on an even byte address or an odd byte address)
Table 3-8 lists the bus cycles performed for each situation
For the timing of A0 and HBE see Section 3 5 5 2
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