NS32FX16-15 Datasheet, PDF (75/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

Appendix A Instruction Formats
NOTATIONS
i e Integer Type Field
B e 00 (Byte)
W e 01 (Word)
D e 11 (Double Word)
f e Floating-Point Type Field
F e 1 (Std Floating 32 bits)
L e 0 (Long Floating 64 bits)
op e Operation Code
Valid encodings shown with each format
gen gen 1 gen 2 e General Addressing Mode Field
See Section 2 4 2 for encodings
reg e General Purpose Register Number
cond e Condition Code Field
0000 e EQual Z e 1
0001 e Not Equal Z e 0
0010 e Carry Set C e 1
0011 e Carry Clear C e 0
0100 e Higher L e 1
0101 e Lower or Same L e 0
0110 e Greater Than N e 1
0111 e Less or Equal N e 0
1000 e Flag Set F e 1
1001 e Flag Clear F e 0
1010 e LOwer L e 0 and Z e 0
1011 e Higher or Same L e 1 or Z e 1
1100 e Less Than N e 0 and Z e 0
1101 e Greater or Equal N e 1 or Z e 1
1110 e (Unconditionally True)
1111 e (Unconditionally False)
short e Short Immediate Value May contain
quick Signed 4-bit value in MOVQ ADDQ
CMPQ ACB
cond Condition Code (above) in Scond
areg CPU Dedicated Register in LPR SPR
0000 e UPSR
0001 – 0111 e (Reserved)
1000 e FP
1001 e SP
1010 e SB
1011 e (Reserved)
1100 e (Reserved)
1101 e PSR
1110 e INTBASE
1111 e MOD
Options in String Instructions
UW B T
T e Translated
B e Backward
U W e 00 None
01 While Match
11 Until Match
Configuration bits in SETCFG instruction
CMFI
7
0
Bcond (BR)
cond
Format 0
1010
7
0
BSR
RET
CXP
RXP
RETT
RETI
SAVE
RESTORE
15
op
Format 1
0000
0001
0010
0011
0100
0101
0110
0111
ENTER
EXIT
NOP
WAIT
DIA
FLAG
SVC
BPT
87
0010
1000
1001
1010
1011
1100
1101
1110
1111
0
gen
short
op
ADDQ
CMPQ
SPR
Scond
Format 2
000
ACB
001
MOVQ
010
LPR
011
15
87
11 i
100
101
110
0
gen
op 1 1 1 1 1 i
Format 3
CXPD
0000
BICPSR
0010
JUMP
0100
BISPSR
0110
Trap (UND) on XXX1 1000
ADJSP
JSR
CASE
1010
1100
1110
15
87
0
ADD
CMP
BIC
ADDC
MOV
OR
gen 1
gen 2
Format 4
0000
0001
0010
0100
0101
0110
SUB
ADDR
AND
SUBC
TBIT
XOR
op
i
1000
1001
1010
1100
1101
1110
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