NS32FX16-15 Datasheet, PDF (19/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

2 0 Architectural Description (Continued)
2 5 GRAPHICS SUPPORT
The following sections provide a brief description of the
NS32FX16 graphics support capabilities Basic discussions
on frame buffer addressing and BITBLT operations are also
provided More detailed information on the NS32FX16
graphics support instructions can be found in the
NS32CG16 Printer Display Processor Programmer’s Refer-
ence
2 5 1 Frame Buffer Addressing
There are two basic addressing schemes for referencing
pixels within the frame buffer Linear and Cartesian (or x-y)
Linear addressing associates a single number to each pixel
representing the physical address of the corresponding bit
in memory Cartesian addressing associates two numbers
to each pixel representing the x and y coordinates of the
pixel relative to a point in the Cartesian space taken as the
origin The Cartesian space is generally defined as having
the origin in the upper left A movement to the right increas-
es the x coordinate a movement downward increases the y
coordinate
The correspondence between the location of a pixel in the
Cartesian space and the physical (BIT) address in memory
is shown in Figure 2-14 The origin of the Cartesian space
(xe0 ye0) corresponds to the bit address ‘ORG’ Incre-
menting the x coordinate increments the bit address by one
Incrementing the y coordinate increments the bit address by
an amount representing the warp (or pitch) of the Cartesian
space Thus the linear address of a pixel at location (x y) in
the Cartesian space can be found by the following expres-
sion
ADDR e ORG a y WARP a x
Warp is the distance (in bits) in the physical memory space
between two vertically adjacent bits in the Cartesian space
Example 1 below shows two NS32FX16 instruction se-
quences to set a single pixel given the x and y coordinates
Example 2 shows how to create a fat pixel by setting four
adjacent bits in the Cartesian space
Example 1 Set pixel at location (x y)
Setup R0 x coordinate
R1 y coordinate
Instruction Sequence 1
MULD
ADDD
SBITD
WARP R1
R0 R1
R1 ORG
Y*WARP
0 X 4 BIT OFFSET
SET PIXEL
Instruction Sequence 2
INDEXD R1 (WARP-1) R0
SBITD R1 ORG
Y*WARP 0 X
SET PIXEL
Example 2 Create fat pixel by setting bits at locations
(x y) (xa1 y) (x ya1) and (xa1 ya1)
Setup R0 x coordinate
R1 y coordinate
Instruction Sequence
INDEXD R1 (WARP-1) R0
SBITD 41 ORG
BIT ADDRESS
SET FIRST PIXEL
ADDQD 1 R1
SBITD R1 ORG
(X01 Y)
SECOND PIXEL
ADDD (WARP-1) R1
SBITD R1 ORG
(X Y01)
THIRD PIXEL
ADDQD 1 R1
SBITD R1 ORG
(X01 Y01)
LAST PIXEL
TL EE 10818 – 5
FIGURE 2-14 Correspondence between
Linear and Cartesian Addressing
2 5 2 BITBLT Fundamentals
BITBLT BIT-aligned BLock Transfer is a general operator
that provides a mechanism to move an arbitrary size rectan-
gle of an image from one part of the frame buffer to another
During the data transfer process a bitwise logical operation
can be performed between the source and the destination
data BITBLT is also called RasterOp operations on rasters
It defines two rectangular areas source and destination
and performs a logical operation (e g AND OR XOR) be-
tween these two areas and stores the result back to the
destination It can be expressed in simple notation as
x Source op Destination Destination
op AND OR XOR etc
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