NS32FX16-15 Datasheet, PDF (4/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

List of Illustrations (Continued)
B B Instructions Format
2-17
BITWT Instruction Format
2-18
EXTBLT Instruction Format
2-19
MOVMPi Instruction Format
2-20
TBITS Instruction Format
2-21
SBITS Instruction Format
2-22
SBITPS Instruction Format
2-23
Bus Activity for a Simple BITBLT Operation
2-24
Operating States
3-1
Slave Processor Protocol
3-2
Slave Processor Status Word
3-3
Interrupt Dispatch Table
3-4
Exception Acknowledge Sequence
3-5
Return from Trap (RETTn) Instruction Flow
3-6
Return from Interrupt (RETI) Instruction Flow
3-7
Interrupt Control Unit Connections (16 Levels)
3-8
Cascaded Interrupt Control Unit Connections
3-9
Exception Processing Flowchart
3-10
Service Sequence
3-11
DSP Module Block Diagram
3-12
Memory Organization of a Complex Vector
3-13
Power and Ground Connections
3-14
Crystal Interconnections 30 MHz
3-15
Crystal Interconnections 40 MHz 50 MHz
3-16
Recommended Reset Connections
3-17
Power-On Reset Requirements
3-18
General Reset Timings
3-19
Bus Connections
3-20
Read Cycle Timing
3-21
Write Cycle Timing
3-22
Cycle Extension of a Read Cycle
3-23
Special Bus Cycle Timing
3-24
Slave Processor Read Cycle
3-25
Slave Processor Write Cycle
3-26
NS32FX16 and FPU Interconnections
3-27
Memory Interface
3-28
HOLD Timing Bus Initially Idle
3-29
HOLD Timing Bus Initially Not Idle
3-30
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