NS32FX16-15 Datasheet, PDF (70/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

4 0 Device Specifications (Continued)
TL EE 10818 – 47
Note 1 ADS must be deactivated before state T4 of the external DMA controller cycle
Note 2 During an external DMA cycle WAIT1–2 must be kept inactive unless they are monitored by the DMA Controller An external DMA cycle is similar to a CPU
cycle The NS32FX16 generates TSO RD WR ALE and DBE The external DMA controller drives the address data lines HBE ADS and DDIN
Note 3 During an external DMA cycle if the ADS signal is pulsed in order to initiate a bus cycle the HOLD signal must remain asserted until state T4 of the DMA
cycle
FIGURE 4-9 External DMA Controller Bus Cycle
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