NS32FX16-15 Datasheet, PDF (73/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

4 0 Device Specifications (Continued)
FIGURE 4-16 INT Signal Timing
Note 1 Once INT is asserted it must remain asserted until it is acknowledged
Note 2 INTA is the Interrupt Acknowledge bus cycle (not a CPU signal) Refer to Section 3 4 1 and Table 3 4
TL EE 10818 – 54
FIGURE 4-17 NMI Signal Timing
TL EE 10818 – 55
FIGURE 4-18 Power-On Reset
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TL EE 10818 – 56