NS32FX16-15 Datasheet, PDF (23/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

2 0 Architectural Description (Continued)
This instruction can be used within the inner loop of a block
OR operation Its use assumes that the source data is
‘clean’ and does not need masking The BITWT format is
shown in Figure 2-18
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87
0
00 0 0 0 0 0 0 0 0 1 00001 0 000 1 1 1 0
FIGURE 2-18 BITWT Instruction Format
External BITBLT
Syntax EXTBLT
Setup
R0 base addresses source data
R1 base address destination data
R2 width (in bytes)
R3 height (in lines)
R4 horizontal increment decrement
R5 temporary register (current width)
R6 source warp (adjusted)
R7 destination warp (adjusted)
Note 1 R0 and R1 are updated after execution to point to the last source
and destination addresses plus related warps R2 R3 and R5 will
be modified R4 R6 and R7 are returned unchanged
Note 2 Source and destination pointers should point to word-aligned oper-
ands to maximize speed and minimize external interface logic
This instruction performs an entire BITBLT operation in con-
junction with an external BITBLT Processing Unit (BPU)
The external BPU Control Register should be loaded by the
software before the instruction is executed (refer to the
DP8510 or DP8511 data sheets for more information on the
BPU) The NS32FX16 generates a series of source read
destination read and destination write bus cycles until the
entire data block has been transferred The BITBLT opera-
tion can be performed in either horizontal direction As con-
trolled by the sign of the contents of register R4
Depending on the relative alignment of the source and des-
tination blocks an extra source read may be required at the
beginning of each scan line to load the pipeline register in
the external BPU The L bit in the PSR register determines
whether the extra source read is performed If L is 1 no
extra read is performed The instructions CMPQB 2 1 or
CMPQB 1 2 could be executed to provide the right setting
for the L bit just before executing EXTBLT Figure 2-19
shows the EXTBLT format The bus activity for a simple
BITBLT operation is shown in Figure 2-24
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87
0
0 0 000 0 000 0 010 1 110 0 0 0 1 1 1 0
FIGURE 2-19 EXTBLT Instruction Format
2 5 3 2 Pattern Fill
Only one instruction is in this group It is usually used for
clearing RAM and drawing patterns and lines
Move Multiple Pattern
Syntax MOVMPi
Setup
R0 base address of the destination
R1 pointer increment (in bytes)
R2 number of pattern moves
R3 source pattern
Note R1 and R3 are not modified by the instruction R2 will always be
returned as zero R0 is modified to reflect the last address into which
a pattern was written
This instruction stores the pattern in register R3 into the
destination area whose address is in register R0 The pat-
tern count is specified in register R2 After each store oper-
ation the destination address is changed by the contents of
register R1 This allows the pattern to be stored in rows in
columns and in any direction depending on the value and
sign of R1 The MOVMPi instruction format is shown in Fig-
ure 2-20
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87
0
000 000 0 0 0 0 0 111 i 0 0 0 0 1 1 1 0
FIGURE 2-20 MOVMPi Instruction Format
2 5 3 3 Data Compression Expansion and Magnify
The three instructions in this group can be used to com-
press data and restore data from compression A com-
pressed character set may require from 30% to 50% less
memory space for its storage
The compression ratio possible can be 50 1 or higher de-
pending on the data and algorithm used TBITS can also be
used to find boundaries of an object As a character is need-
ed the data is expanded and stored in a RAM buffer The
expand instructions (SBITS SBITPS) can also function as
line drawing instructions
Test Bit String
Syntax TBITS option
Setup
R0 base address source (byte address)
R1 starting source bit offset
R2 destination run length limited code
R3 maximum value run length limit
R4 maximum source bit offset
Option 1
0
count set bits until a clear bit is found
count clear bits until a set bit is found
Note R0 R3 and R4 are not modified by the instruction execution R1
reflects the new bit offset R2 holds the result
This instruction starts at the base address adds a bit offset
and tests the bit for clear if ‘‘option’’ e 0 (and for set if
‘‘option’’ e 1) If clear (or set) the instruction increments to
the next higher bit and tests for clear (or set) This testing
for clear proceeds through memory until a set bit is found or
until the maximum source bit offset or maximum run length
value is reached The total number of clear bits is stored in
the destination as a run length value
When TBITS finds a set bit and terminates the bit offset is
adjusted to reflect the current bit address Offset is then
ready for the next TBITS instruction with ‘‘option’’ e 0 After
the instruction is executed the F flag is set to the value of
the bit previous to the bit currently being pointed to (i e the
value of the bit on which the instruction completed execu-
tion) In the case of a starting bit offset exceeding the maxi-
mum bit offset (R1 ^t R4) the F flag is set if the option was
1 and clear if the option was 0 The L flag is set when the
desired bit is found or if the run length equalled the maxi-
mum run length value and the bit was not found It is cleared
otherwise Figure 2-21 shows the TBITS instruction format
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87
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000 000 0 0 S 0 1 001 110 0 0 0 1 1 1 0
 S is set for ‘TBITS 1’ and clear for ‘TBITS 0’
FIGURE 2-21 TBITS Instruction Format
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