NS32FX16-15 Datasheet, PDF (13/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

2 0 Architectural Description (Continued)
2 4 2 Addressing Modes
The NS32FX16 CPU generally accesses an operand by cal-
culating its Effective Address based on information avail-
able when the operand is to be accessed The method to be
used in performing this calculation is specified by the pro-
grammer as an ‘‘addressing mode ’’
Addressing modes in the NS32FX16 are designed to opti-
mally support high-level language accesses to variables In
nearly all cases a variable access requires only one ad-
dressing mode within the instruction that acts upon that
variable Extraneous data movement is therefore minimized
NS32FX16 Addressing Modes fall into nine basic types
Register The operand is available in one of the eight Gen-
eral Purpose Registers In certain Slave Processor instruc-
tions an auxiliary set of eight registers may be referenced
instead
Register Relative A General Purpose Register contains an
address to which is added a displacement value from the
instruction yielding the Effective Address of the operand in
memory
Memory Space Identical to Register Relative above ex-
cept that the register used is one of the dedicated registers
PC SP SB or FP These registers point to data areas gen-
erally needed by high-level languages
Memory Relative A pointer variable is found within the
memory space pointed to by the SP SB or FP register A
displacement is added to that pointer to generate the Effec-
tive Address of the operand
Immediate The operand is encoded within the instruction
This addressing mode is not allowed if the operand is to be
written
Absolute The address of the operand is specified by a
displacement field in the instruction
External A pointer value is read from a specified entry of
the current Link Table To this pointer value is added a dis-
placement yielding the Effective Address of the operand
Top of Stack The currently-selected Stack Pointer (SP0 or
SP1) specifies the location of the operand The operand is
pushed or popped depending on whether it is written or
read
Scaled Index Although encoded as an addressing mode
Scaled Indexing is an option on any addressing mode ex-
cept Immediate or another Scaled Index It has the effect of
calculating an Effective Address then multiplying any Gen-
eral Purpose Register by 1 2 4 or 8 and adding into the
total yielding the final Effective Address of the operand
Table 2-1 is a brief summary of the addressing modes For a
complete description of their actions see the Series 32000
Instruction Set Reference Manual
In addition to the general modes Register-Indirect with
auto-increment decrement and warps or pitch are available
on several of the graphics instructions
Byte Displacement Range b64 to a63
Word Displacement Range b8192 to a8191
Double Word Displacement
Range (Entire Addressing Space)
FIGURE 2-13 Displacement Encodings
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