NS32FX16-15 Datasheet, PDF (43/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

3 0 Functional Description (Continued)
The cases shown assume that the selected memory or pe-
ripheral device is capable of communicating with the CPU at
full speed If not then cycle extension may be requested
through CWAIT and or WAIT1– 2
A full-speed bus cycle is performed in four cycles of the
CTTL clock signal labeled T1 through T4 Clock cycles not
associated with a bus cycle are designated Ti (for ‘‘idle’’)
During T1 the CPU applies an address on pins AD0 – AD15
and A16 –A23 and provides a low-going pulse on the ADS
pin which serves the dual purpose of informing external
circuitry that a bus cycle is starting and of providing control
to an external latch for demultiplexing Address bits 0 – 15
from the AD0 – AD15 pins It also deasserts the ALE signal
which eliminates the need to invert ADS to generate the
strobe for the address latches See Figure 3-20 During this
time also the status signals DDIN indicating the direction of
the transfer and HBE indicating whether the high byte
(AD8 – AD15) is to be referenced become valid
During T2 the CPU switches the Data Bus AD0 – AD15 to
either accept or present data Note that the signals A16 –
A23 remain valid and need not be latched
FIGURE 3-20 Bus Connections
TL EE 10818 – 28
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