NS32FX16-15 Datasheet, PDF (10/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

2 0 Architectural Description (Continued)
OPC Operation Code Specifies the vector operation to be
performed
x OPC e 00 VCMAD Vector Complex Multiply Add
x OPC e 01 VCMUL Vector Complex Multiply
x OPC e 10 VCMAC Vector Complex Multiply
Accumulate
x OPC e 11 VCMAG Vector Complex Magnitude
ST Status Register ST is a read-only register that holds
the status of the last vector operation The format of the ST
register is shown in Figure 2 7
7
0
OVF X X X X X OP1 OP0
FIGURE 2-7 ST Register Format
OP0 Overflow occurred on calculation of A0
OP1 Overflow occurred on calculation of A1
OVF Overflow indication
The ST register is cleared to 0 in the following cases
the user writes directly to either A0 or A1
the user writes to the CTL register
upon reset
2 1 6 RAM Array
The on-chip RAM array provides 384 bytes of storage that is
used to store up to 96 32-bit complex numbers These num-
bers represent the coefficients C 0 – C 95 used by the
DSP Module
During a vector operation the DSP Module accesses these
coefficients sequentially starting with the coefficient indexed
by the STRT field in the CPTR register
The RAM array is not limited to coefficient storage only It
can be used as a fast zero wait-state on-chip memory for
instructions and data storage
RAM array accesses must be word or double-word aligned
Failing to do so may cause unpredictable results Figure 2-8
shows the RAM array address map
Complex
Coefficients
31
0
C0



C 95
Coefficient
Addresses
FFFFD000



FFFFD17C
FIGURE 2-8 On-Chip RAM Array Address Map
2 2 MEMORY ORGANIZATION
The main memory of the NS32FX16 is a uniform linear ad-
dress space Memory locations are numbered sequentially
starting at zero and ending at 2²⁴ b 1 The number specify-
ing a memory location is called an address The contents of
each memory location is a byte consisting of eight bits Un-
less otherwise noted diagrams in this document show data
stored in memory with the lowest address on the right and
the highest address on the left Also when data is shown
vertically the lowest address is at the top of a diagram and
the highest address at the bottom of the diagram When bits
are numbered in a diagram the least significant bit is given
the number zero and is shown at the right of the diagram
Bits are numbered in increasing significance and toward the
left
7
0
A
Byte at Address A
Two contiguous bytes are called a word Except where not-
ed the least significant byte of a word is stored at the lower
address and the most significant byte of the word is stored
at the next higher address In memory the address of a
word is the address of its least significant byte and a word
may start at any address
15
87
0
Aa1
A
MSB
LSB
Word at Address A
Two contiguous words are called a double-word Except
where noted the least significant word of a double-word is
stored at the lowest address and the most significant word
of the double-word is stored at the address two higher In
memory the address of a double-word is the address of its
least significant byte and a double-word may start at any
address
31
24 23
16 15
87
0
Aa3
Aa2
Aa1
A
MSB
LSB
Double Word at Address A
Although memory is addressed as bytes it is actually orga-
nized as words Therefore words and double-words that are
aligned to start at even addresses (multiples of two) are
accessed more quickly than words and double-words that
are not so aligned
2 2 1 Address Mapping
The NS32FX16 supports the use of memory-mapped pe-
ripheral devices and coprocessors Such memory-mapped
devices can be located at arbitrary locations within the 16-
Mbyte address range available externally
The address range from 01000000 (hex) to FF800000 (hex)
is not available in the present implementation of the
NS32FX16 and should not be used The top 8-Mbyte block
is reserved by National Semiconductor Corporation and
only a few locations within this block are presently used to
access the on-chip RAM array and DSP Module control reg-
isters Figure 2-9 shows the NS32FX16 address mapping
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