NS32FX16-15 Datasheet, PDF (86/88 Pages) National Semiconductor (TI) – Imaging/Signal Processor

Appendix B Instruction Execution Times (Continued)
TABLE B-3 Average Instruction Execution Times with No Wait-States (Continued)
Instruction
Number of Clock Cycles
Notes
BITWT
16
28
28 a (shift b 8)
Shift e 0
x Shift e 1 8
Shift ^l 8
EXTBLT
35 a (19 a 12
35 a (13 a 12
35 a (17 a 13
35 a (11 a 13
width )
width )
width )
width )
height
height
height
height
x Shift e 0 8 Pre-Read
x Shift e 0 8 No Pre-Read
Shift ^l 8 Pre-Read
Shift ^l 8 No Pre-Read
MOVMPB W
16 a 7 R2
MOVMPD W
16 a 8 R2
SBITS
39
42
R2 ^s 25
R2 ^l 25
SBITP
8 a (34 R2)
Instruction
BBOR
BBXOR
BBAND
BBFOR
BBSTOD
BITWIT
EXTBLT
MOVMPB W
MOVMPD
SBITS
SBITP
TABLE B-4 Average Instruction Execution Times with Wait-States
Number of Clock Cycles
42 a ((107 a 2 Twaitblt) a (44 a Twaitblt) (width b 2)) height
44 a ((107 a 2 Twaitblt) a (44 a Twaitblt) (width b 2)) height
45 a ((111 a 2 Twaitblt) a (44 a Twaitblt) (width b 2)) height
48 a ((74 a 2 Twaitblt) a (32 a Twaitblt) (width b 2)) height
66 a ((170 a 2 Twaitblt) a (60 a Twaitblt) (width b 2)) height
16 a Twaitrds a Twaitrdd a Twaitwrd
28 a Twaitblt
35 a (19 a (12 a (Twaitrds a Twaitrdd a Twaitwrd) ) width ) height
35 a (13 a (12 a (Twaitrds a Twaitrdd a Twaitwrd)) width ) height
16 a 7 R2 a (Twaitwr b 1) R2
16 a 7 R2
16 a 8 R2 a Twaitwr R2
39 a (2 Twaitrdd a 2 Twaitwrd a 2 Twaitrds)
42 a (2 Twaitrdd a 2 Twaitrds)
8 a (34 R2) a ((Twaitrdd a Twaitwrd) R2)
Notes
Shift e 0
x Shift e 1 8
Pre-Read
No Pre-Read
Twaitwr ^l 1
Twaitwr ^s 1
R2 ^s 25
R2 ^l 25
B 3 DSPM INSTRUCTIONS
A DSPM instruction execution starts with the CPU core writ-
ing to the CTL register The execution time is counted from
state T3 of this transaction until all the results are ready
either in the accumulator or in the coefficient RAM array
The execution times in clock cycles for the various DSPM
instructions are listed in Table B-5
It is assumed that External Hold Requests do not occur in
the middle of a VCMAD VCMUL or VCMAC instruction
The parameters n and w represent the number of elements
in the vector instruction and the number of wait states ap-
plied to each DSPM bus transaction respectively
TABLE B-5 DSPM Instruction Execution Times
Instruction
Number of Clock Cycles
VCMAD
VCMUL
VCMAC
VCMAG
9a8 na2 n w
9a8 na2 n w
6a8 na2 n w
5a8 n
86